HP 3000 III Series Manual page 330

Inte rr upt Sys tern
used to prevent a dispatch during critical sections of code and
to avoid unnecessarily restarting the Dispatcher. If the DISP
instruction is executed and tqe Dispatcher is disabled (QI-18 is
non-zero), then bit 0 of QI is set to 1 and the next CPU instruc-
tion is fetched. This bit is reset either by IXIT or PSEB when
QI-18 becomes zero. If QI-18 is already zero at the start of a
PSEB instruction, a system halt will occur.
8-54. IXIT Instruction
Figure 4-13 is a simplified flowchart of the IXIT instruction.
IXIT operates in either of two ways. The first is by the Dis-
patcher to transfer to a process being launched (1, figure 4-l3).
The second (2) through (6), is to exit from ICS type interrupt
routines. If the interrupt service routine is not in segment
number 1, it is assumed to be an external interrupt routine and a
Reset Interrupt is sent to the device whose device number is in
Q+3. If bit
0
of Q is zero and if Q=QI, the return is to the
interrupted process (2). Otherwise the return is to a lower pri-
ority interrupt which was interrupted (3). If bit 0 of Q is 1
and bit
0
of QI is zero, the return is to the Dispatcher which
was interrupted (4). If both bit 0 of Q and bit 0 of QI are 1, a
DISP instruction has been executed and the request to start the
Dispatcher is still pending. If QI-18 is zero, the Dispatcher is
not disabled, QI is cleared, and a transfer is made to the Dis-
patcher's entry point (5) or (6). It does not matter whether a
process (Q=QI) or the Dispatcher (Q not equal to QI) was inter-
rupted. If QI-18 is non-zero, the Dispatcher is disabled and the
DISP request cannot be carried out at this time. Instead, IXIT
returns to the interrupted Dispatcher (Q not equal to QI (4a}),
or to the interrupted process (Q = QI (2a}). The Start Dispatch-
er request is still pending, (bit 0 of QI is
I).
8-55. INTERRUPT SYSTEM SERVICING INFORMATION
Except for checking the' interrupt poll line for proper installa-
tion, no repair procedures are required for the interrupt system.
As previously discussed, the interrupt priority of a divice is
determined by the device's logical proximity to the lOP on a
jumpered interrupt poll line. The interrupt poll line is wired
during system configuration from the lOP to whatever device is
assigned first priority and then from device to device according
to assigned priority. The interrupt poll line terminates at the
device of lowest priority.
The interrupt poll line for any system starts at connector pins
79
(INTPOLL) and 80 (GND) of connector 10Pl of the CPU/lOP back-
plane. The interrupt poll line consists of a twisted pair of
wires; one blue wire and one white wire. This twisted pair is
terminated at each end with a two-pin spring-clip connector that
clips onto pairs of vertically-aligned connector pins. At the
CPU/lOP backplane, the twisted pair must be installed with the
white wire connected to the top pin of the two vertically-aligned
pins. At the device controller interface PCA's, the twisted pair
must be installed with the white wire connected to the bottom pin
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