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System/CPU Overview
(2) For SPECOP 01 through 17 (CrR (4:7)
=
%01 - %17), the
W-
bit causes the same action as in paragraph c above.
e.
SUBOP %04 through %17
(eIR
(0: 3)
=
%04
%1 7)
instructions
generally
reference
an
operand
in memory.
The operations
necessary to obtain the effective address is this operand are
common to most of the instructions and, therefore, one micro-
program is
used for this calaculation.
When
one of
these
instructions
is to
be executed, it maps
through the LVT to
this microprogram to
obtain the operand address.
When this
is
done,
the instruction then jumps to the microprogram that
executes the specified instruction and the W-bit now
becomes
effective.
The W-bit is set to logic 1.
When the foregoing
address calculation routine
has
been
completed,
a
micro-
operation
(JLUI)
in the ROM Skip field is executed.
If the
instruction does not specify indirect addressing
or
if
one
level
of
indirect addressing has been completed, the execu-
tion of
JULI
forces
a
microprogram
jump
to
an
address
contained in the LUT.
Since the contents of the CIR have not
changed, the LUT would normally
still
be
pointing
to
the
address
of
the foregoing address calculation routine and an
infinite loop would result.
However, the W-bit now
modifies
the
LUT
entry address to a different, but related, address.
This LUT address contains the
microprogram
address
of
the
desired instruction to be executed.
2-81.
VBUS MUX AND VBUS CONTROL.
One of the nine inputs to
the
VBUS
MUX is
selected by the VBUS
Control to be fed through the
VBUS MUX which becomes a 16-bit
address for the
ROM.
This ad-
dress
is also applied to the
Incrementor (INC) which increments
the address by
one and applies
this new address to the
ROM Ad-
dres s Re g iste r
(RAR).
2-82. RAR. The RAR is a 16-bit register that holds the address of
fue
next microinstruction to be executed if no preempting condi-
tions (interrupt, jump, etc.) occur.
The RAR is loaded with
the
ROM address
incremented by one and is
automatically incremented
every 175
nanoseconds by the INC until the end of
the micropro-
gram for the instruction is reached.
Normally, the RAR is loaded
from the INC.
However, if a repeat is specified, the contents of
fue RAR does not
change until the repeat is terminated.
In ad-
dition
to the
12-bit output
from the LUT ROM,
the RAR
can he
loaded from the ROM Output
Register Rank 2 (ROR2), by a
JMPGATE
signal
generated in response to a Function field code Jump (JMP)
or Jump
.'Ib
Subroutine (JSB),
by the interrupt
logic
due to
an
interrupt
or power failure, from the V-Bus in response to an RAR
store specified, or from the Hardware Ma intenance Panel.
2-83.
SAVE REGISTER. When a JSB is decoded by the Function Field
Decoder,
a
JSBI signal is generated and the contents of the RAR
is loaded
into the Save Register until a Return
from Subroutine
(RSB) is decoded by the Skip Field Decoder.
The RSB signal Loads
fue contents of the Sa ve Register back into the VBUS MUX and from
there
back into the ROM which continues executing
the micropro-
gram with the microinstruction folLowing the JSB.
2-52
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