HP 3000 III Series Manual page 86

System/CPU Overview
skipped were already clocked into the R- and S-Bus Registers so
that the data on the U-Bus at the end of the NOP cycle is the sum
of the contents of the source registers.
2-86. Microcode Jumps. Microcode jumps can be taken from either
RORI or ROR2. The jumps can be taken from RORI only under the
condition that the jump has an unconditional skip code and the
instruction in
ROR2
meets one or more of the following condi-
tions: is cancelled by NOP2; is a ROM Immediate type instruction
without a data-dependent skip; contains a NOP skip function;
and/or contains a non-data-dependent skip test (skip codes 14
through 27, 32, 33, and 34) which is not met or if an RORI jump
has just been completed. All other microcode jumps will be ex-
ecuted from ROR2.
An unconditional jump is a jump that occurs without regard to the
data. If the microcode calls for an unconditional jump, a jump
target address is selected out of the Shift, Special, and R-Bus
fields of the microcode instruction in RORI (ROR2 if previous
microcode instruction contained a data-dependent skip condition)
and appl ied back to the VBUS MU X so tha t the new ROM microcode
instruction is sent to RORI. The target address goes to the INC,
is incremented by one, and the new target address plus one is
stored in the RAR until the next clock cycle when it is applied
to the VBUS MUX for consecutive addressing of the microcode in-
s tr uct ions.
The jumps that are executed from ROR2 beca use none of the
fast-jump conditions were present for RORI and the conditional
j LmpS that are always executed fr om ROR2 behave as follows: Not
Taken, next line in sequence executed on next clock;
Non-Data-Dependent Taken, one overhead clock required (NOP2 ef-
fective) before target line executed; Data-Dependent Taken, two
overhead clocks required (FREEZE, NOP2) before target line ex-
ecuted. Execution of jumps in IDR2 inhib it any fast jumps from
RORI being executed. Therefore, if there are two consecutive
lines of microcode containing jumps, the jump in
ROR2
will be
taken and the jump in RORI will be ignored.
The microcode instruction calling for a jump comes out of ROM and
into RORI which decodes the R- and S-Bus fields as discussed in
paragraph 2-85. The R- and S-Bus field information is sent
through the R- and S-Bus Logic and is waiting at the inputs of
the R- and S-Bus Registers. On the next clock cycle, the jump
instr uction goes to ROR2 and the R- and S-Bus field da ta is
clocked :through the R- and S-Bus Registers. The T-Bus data is
loaded fr bm ROR2 to feed ROM so that, on the next clock cycle,
the address of the jump-to-microcode instruction goes to ROM. As
the new instruction is clocked into ROR2, the jump-to-microcode
address plus one goes into the RAR and the operation resumes
stepping through the microcode.
2-54