HP 3000 III Series Manual page 165

Machine Instr uctionsand Stack cpera tions
tions, on the other hand, transfer only one word per instruction,
between the device and the TOS in the cpu.
An SIO type data transfer is initiated by the cpu executing a
Start I/O instruction for a particular device. The instruction
assumes that there is an I/O program stored in main memory. The
hardware I/O system executes the I/O program independently of the
cPU. The cpu is then free to continue processing in parallel
with the I/O operations.
Figure 4-14 illustrates the order pair format of the double words
which are used in I/O programs. The general format is shown at
the top of the figure and then the actual format of each of the
nine orders is shown beneath, The first word of an order pair is
designated as the I/O Command Wbrd, or IOCW, and the second word
is designated as the I/O Address Word, or IOAW. The IOAW does
not necessarily always contain an address, as the figure shows.
The nine I/O orders are defined as follows:
JUMP. If bit 4 of the IOCW is a "1", a conditional jump of I/O
program control is made to the address given by the IOAW at the
discretion of the device controller. If bit 4 of the IOCW is a
"0", an uncondi tional jump is made.
RETURN RESIDUE. This causes the residue of the count to be re-
turned to the IOAW. The residue is obtained from the Multiplexer
or Selector Channel. Each Multiplexer or Selector Channel has
its own count. The count is initialized from the least signifi-
cant 12 bits of all IOCWs except Return Residue and Set Bank.
SET BANK. This instruction loads the Bank Register of the Mul-
tiplexer or Selector Channel with bits 12 through 15 of its IOAW.
The execution of an SIO instruction automatically clears the Bank
Register. Therefore, if the data buffer for this device
r~sides
in some bank other than 00, the I/O program must contain a SET
BANK order prior to a READ or WRITE order.
INTERRUPT. This order
its Inte r rupt Reques t
CPU.
pair causes the device controller to set
fl ip- flop and, the re fore, to in te r r upt the
END. End of the I/O p rogr am. If bi t 4 of the IOCW is a "1", the
device controller also interrupts the CPU. Returns device status
to the IOAW.
CONTROL. This causes transfer of a l6-bit control word in the
IOAW to the device controller, as well as the 12 low order bits
of the IOCW.
SENSE. This causes transfer of a l6-bit status word from the
device controller to the IOAW.
4-35