Standard Stack Marker Format - HP 3000 III Series Manual

System/CPU Overview
01 112 ' 31 415 ' 61 7 1 8
1
9110111112113'14115
X
Register Contents
PB Relative Return Address for P Reg
MIIITIRIOICI
cc
I
Code Segment
#
Delta
Q
Figure 2-12. Standard Stack Marker Format
2-31. GENERAL FORMAT. The first format shown in figure 2-13 is
the general scheme for dividing the instruction word into code
fields. Only the first field is rigidly adhered to. This field
(bits 0 through 3) defines either a specific instruction code in
the memory address group (or loop control group) or one of the
sub-\opcode groups. There are four sub-lopcode groups; 1,2,3,
and stack ops. The field for the sub-cpcodes varies. For sub-
opcode groups 2 and 3, bits 4, 5,6, and 7 are used as shown.
For subopcode group 1, bits 5 through 9 are used and, for stack
ops, the remainder of the word is used. In some cases, the sub-
opcode will enable a third field (rnini-opcode or special opcode)
in bits 8 through 11. The remainder of the word has a variety of
special uses and commonly is part of an argument field.
2-32. STACK OPe The stack op format is defined by four O's in
the first four bits. The remaining 12 bits are divided into two
fields; stack op A and stack op B. Either or both of these
fields may contain any of the 63 stack cp instruction codes.
Execution sequence is
from left to right (A first, then E).
In-
terrupts may occur between the execution of A and B. It should
also be noted that indicators (Carry, Overflow, and Cbndition
Code) are set by the last executed statck Ope If using only one
of the two stack op fields, it is more efficient to use stack op
A since the hardware always looks ahead to see if stack op B is a
NOP. This permits the hardware to ignore the second field which
results in saving time.
2-33. SHIFT. The shift instructions use about half of the sub-
opcode group 1 codes. Sub-opcode group 1 is defined by 0001 in
the first four bits. If the index bit (bit 4) is 1, the contents
of the Index register (X Register) is added to the shift count in
bits 10 through 15 to specify the number of places each data bit
is shifted. Bits 5 through 9 encode the specific shift
ins tr uct ion.
2-34. BRANCH. The branch instructions use 11 of the sub-opcode
group 1 codes. Bit 4 is used as an indirect bit (indirect if bit
4 is 1 and direct if bi t 4 is 0) • Bi ts 5 th rough 9 encode the
specific branch instruction. Bits 11 through 15 give a P-rela-
tive displacement from 0 through 31 and bit 10 specifies whether
the displacement is + or - relative to P (0
=
+, 1
= -).
2-28