HP 3000 III Series Manual page 232

MCU/Main Memory Overview
from the MOD Register and pass them to the interrupt handling CPU
instruction. To command the TO ME - FROM ME lines, the CPU in-
struction XEQ takes the l6-bit TOS value and executes it as an
instruction. In order to do this, the value must be placed in
the NIR before it can be gated to the CIR to be executed. Be~·
cause the CTL Bus is the only data path into NIR, the value is
placed on the FROM lines of the CTL Bus with an address of
TO
the
CPU (in essence, TO
ME).
The FROM lines will have the CPU's port
number (FROM ME) •
The TO ME - FROM
ME
action is caused by a code of NIR in the MCU
field of a microinstruction. When the MCU detects the NIR code,
the High Request (CPU HREQ) flip-flop and the Next-In-Process
(NIP) flip-flop (figure 6-1) are set and the value placed on the
U-Bus is clocked into DCOR (figure 2-20). The hardware places a
NOP code in the MOP Register and clocks the FROM jumper value
through TO MUX into the TO Register. The MCU, when granted pri-
ority to use the CTL Bus, gates the contents of the TO, MOP, and
DOOR Registers onto the CTL Bus. Because the MCU for the CPU is
monitoring the CTL Bus at all times, the
TO
Comparator recognizes
that the CPU is being addressed and that the CPU is expecting the
communication (determined by the fact that the values on the FROM
lines match the contents of the TO Register) • The MCU, there-
fore, will accept the value on the MeUD lines and, because the
NIP flip-flop has been set, the value is clocked into NIR. The
same sequence as des cr ibed for TO
ME -
FROM
ME
will occur if an
Operand (OPND) code is decoded in the MCU field of a microin-
str uction. The only difference is that the MCU' s OPINP flip-flop
(figure 6-1) is set instead of the NIP flip-flop and the value
will be gated into the OPND Register instead of the NIR.
6-16. MCU SERVICING INFORMATION
The Central Processor Mbdule MCU PCA is a nonrepairable PCA and
must be replaced if found defective. No repair procedures are
required. However, the MCU, PCA does contain jumpers that must be
properly configured. The jumper configurations are discussed in
paragraphs 6-17 through 6-21 and identified in figure 6-3. (Ser-
vicing information for other computer module MCU circuits is pro-
vided with the discussions of the individual modules.)
6-17. ENABLE. The ENABLE signal is used to establish priority for
accessing the CTL Bus. The insertion of jumpers WI through W4 es-
tablish the priority of the MCU PCA. Jumper WI must be installed.
6-18. READY. The READY signal is used to signify that a module
is ready to communicate with memory. The insertion of jumpers W5
(READY 4) through W7 (READY 6) determine which READY line is as-
signed to the MCU PCA. Jumper W6 (READY 5) must be installed.
6-19. CPU NUMBER. The system is designed to have only one CPU
which must be designated as CPU number 1. Ensure that jumper WID
is installed and that jumper Wll has been removed.
6-8