HP 3000 III Series Manual page 81

System/CPU Overview
'I'he entire data calculation is accomplished by one microcode in-
struction which is also executed in two steps. During the first
step, the microcode instruction is held in RORI. Effectively,
the only two microcode instruction fields being decoded during
this clock cycle are the R- and S-Bus fields. (Refer to Section V
for microcode instruction format descriptions.) These two fields
cause the R- and S-Bus Logic to select the correct registers for
the two operands and gate the operands to the R- and S-Bus Reg-
isters. The same clock cycle that gates the operands into the
R- and S-Bus Registers also gates the current microcode instr"uc-
tion into ROR2 and gates the next microcode instruction into RORI
as discussed in paragraph 2-74. It also gates the previous mic-
rocode instructions's final result into the register specified
by
the instruction's Store field. During the second step (current
microcode instruction in ROR2) ,the instruction's Function field
specifies what calculation is to be accomplished by selecting
either the Shifter or Decimal Corrector and the instr uction'-s
Shift field specifies what the Shifter or Decimal Corrector is to
accomplish. Also, the instruction's Store field specifies to the
Store Logic which register to select to gate the final result
appearing on the U-Bus. During the next clock cycle, the now
cQ~pleted
microcode instruction is discarded by loading the next
microcode instruction into ROR2 and the final result of the exe-
cuted instruction is gated into the register specified by the
Store Logi c.
Each microcode instruction also contains two other fields that
are decoded during execution; a Skip field and a Special field.
The Special field controls the hardware that performs such oper-
ations as setting condition codes, popping the stack, and incre-
menting and decrementing the stack's SR Register. A complete
listing of the operations specified by the Special field is con-
tained in Section V. The Skip field specifies test conditions
such as the status of internal flags, the contents of the
SR Register as compared to zero through four, and operand results
that appear on the T-Bus as compared to zero, non-zero, odd, and
even. A
c~nplete
listing of the test conditions specified
by
the
Skip field is contained in Section V. The Skip field determines
which condition will be tested for a possible skip. If the con-
dition is met
1
ROR2 executes a No Operation (NOP), effectively
skipping one microinstruction word. Other signals, such as NEXT,
also come from the Skip field.
2-74. MI CROCODE PIPELINE. In general, the microcode pipeline
r ece i ves a reques ted ins tr uct ion from l\la in Memor y v i a the CrL
Bus, MC U, and
Ne
x tIn s t rue t ion Re g i s te r (N I R) • Se e fig u r e 2- 2 0 •
The instruction is clocked into the CIR and then into the CMUX.
If the pipeline has not been previously filled, the NIR output is
clocked into the CIR and CMUX simultaneously, thus saving one
clock cycle. Ten bits of the CMUX output go to the Mapper and 8
bits go to the Mapper Control. The 8-bit output of the Mapper
goes to the Look Up Table (LUT) ROM. The LUT ROM produces a
12-bit microprogram starting address from the received instruc-
tion and also eight special use bits. The SRPO, SRPl, and SRP2
special use bits go to the SR Preadjust Adder. The Z, PCO, PCl,
2-49