Philips LPC2119 User Manual page 114

Philips Semiconductors
ARM-based Microcontroller
The UART0 RLS interrupt (U0IIR3:1=011) is the highest priority interrupt and is set whenever any one of four error conditions
occur on the UART0 Rx input: overrun error (OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART0 Rx
error condition that set the interrupt can be observed via U0LSR4:1. The interrupt is cleared upon an U0LSR read.
The UART0 RDA interrupt (U0IIR3:1=010) shares the second level priority with the CTI interrupt (U0IIR3:1=110). The RDA is
activated when the UART0 Rx FIFO reaches the trigger level defined in U0FCR7:6 and is reset when the UART0 Rx FIFO depth
falls below the trigger level. When the RDA interrupt goes active, the CPU can read a block of data defined by the trigger level.
The CTI interrupt (U0IIR3:1=110) is a second level interrupt and is set when the UART0 Rx FIFO contains at least one character
and no UART0 Rx FIFO activity has occurred in 3.5 to 4.5 character times. Any UART0 Rx FIFO activity (read or write of UART0
RSR) will clear the interrupt. This interrupt is intended to flush the UART0 RBR after a message has been received that is not a
multiple of the trigger level size. For example, if a peripheral wished to send a 105 character message and the trigger level was
10 characters, the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts
(depending on the service routine) resulting in the transfer of the remaining 5 characters.
Table 81: UART0 Interrupt Handling
U0IIR[3:0] Priority
0001 -
0110 Highest
0100 Second
1100 Second
0010 Third
note: values "0000", "0011", "0101", "0111", "1000", "1001", "1010", "1011","1101","1110","1111" are reserved.
The UART0 THRE interrupt (U0IIR3:1=001) is a third level interrupt and is activated when the UART0 THR FIFO is empty
provided certain initialization conditions have been met. These initialization conditions are intended to give the UART0 THR FIFO
a chance to fill up with data to eliminate many THRE interrupts from occurring at system start-up. The initialization conditions
implement a one character delay minus the stop bit whenever THRE=1 and there have not been at least two characters in the
U0THR at one time since the last THRE=1 event. This delay is provided to give the CPU time to write data to U0THR without a
THRE interrupt to decode and service. A THRE interrupt is set immediately if the UART0 THR FIFO has held two or more
characters at one time and currently, the U0THR is empty. The THRE interrupt is reset when a U0THR write occurs or a read of
the U0IIR occurs and the THRE is the highest interrupt (U0IIR3:1=001).
UART0
Interrupt
Type
none none
Rx Line Status /
OE or PE or FE or BI
Error
Rx Data
Rx data available or trigger level reached in FIFO (U0FCR0=1)
Available
Minimum of one character in the Rx FIFO and no character
input or removed during a time period depending on how many
characters are in FIFO and what the trigger level is set at (3.5
Character Time-
to 4.5 character times).
out Indication
The exact time will be:
[(word length) X 7 - 2] X 8 + {(trigger level - number of
characters) X 8 + 1] RCLKs
THRE
LPC2119/2129/2292/2294
Interrupt
Source
THRE
114
Preliminary User Manual
Interrupt
Reset
-
U0LSR Read
U0RBR Read or
UART0 FIFO
drops below
trigger level
U0 RBR Read
U0IIR Read (if
source of
interrupt) or
THR write
January 08, 2004