Register Description - Philips LPC2119 User Manual

Philips Semiconductors
ARM-based Microcontroller

REGISTER DESCRIPTION

The VIC implements the registers shown in Table 40. More detailed descriptions follow.
Table 40: VIC Register Map
Address Name
0xFFFF F000 VICIRQStatus
0xFFFF F004 VICFIQStatus
0xFFFF F008 VICRawIntr
0xFFFF F00C VICIntSelect
0xFFFF F010 VICIntEnable
0xFFFF F014 VICIntEnClr
0xFFFF F018 VICSoftInt
0xFFFF F01C VICSoftIntClear
0xFFFF F020 VICProtection
0xFFFF F030 VICVectAddr
0xFFFF F034 VICDefVectAddr
0xFFFF F100 VICVectAddr0
0xFFFF F104 VICVectAddr1
0xFFFF F108 VICVectAddr2
0xFFFF F10C VICVectAddr3
0xFFFF F110 VICVectAddr4
0xFFFF F114 VICVectAddr5
0xFFFF F118 VICVectAddr6
0xFFFF F11C VICVectAddr7
0xFFFF F120 VICVectAddr8
0xFFFF F124 VICVectAddr9
Vectored Interrupt Controller (VIC)
IRQ Status Register. This register reads out the state of those interrupt
requests that are enabled and classified as IRQ.
FIQ Status Requests. This register reads out the state of those interrupt
requests that are enabled and classified as FIQ.
Raw Interrupt Status Register. This register reads out the state of the 32
interrupt requests / software interrupts, regardless of enabling or
classification.
Interrupt Select Register. This register classifies each of the 32 interrupt
requests as contributing to FIQ or IRQ.
Interrupt Enable Register. This register controls which of the 32 interrupt
requests and software interrupts are enabled to contribute to FIQ or
IRQ.
Interrupt Enable Clear Register. This register allows software to clear
one or more bits in the Interrupt Enable register.
Software Interrupt Register. The contents of this register are ORed with
the 32 interrupt requests from various peripheral functions.
Software Interrupt Clear Register. This register allows software to clear
one or more bits in the Software Interrupt register.
Protection enable register. This register allows limiting access to the VIC
registers by software running in privileged mode.
Vector Address Register. When an IRQ interrupt occurs, the IRQ service
routine can read this register and jump to the value read.
Default Vector Address Register. This register holds the address of the
Interrupt Service routine (ISR) for non-vectored IRQs.
Vector address 0 register. Vector Address Registers 0-15 hold the
addresses of the Interrupt Service routines (ISRs) for the 16 vectored
IRQ slots.
Vector address 1 register
Vector address 2 register
Vector address 3 register
Vector address 4 register
Vector address 5 register
Vector address 6 register
Vector address 7 register
Vector address 8 register
Vector address 9 register
LPC2119/2129/2292/2294
Description
77
Preliminary User Manual
Reset
Access
Value*
RO 0
RO 0
RO 0
R/W 0
R/W 0
W 0
R/W 0
W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
January 08, 2004