Philips LPC2119 User Manual page 60

Philips Semiconductors
ARM-based Microcontroller
Table 24: PLL Status Register (PLLSTAT - 0xE01FC088)
PLLSTAT Function
4:0 MSEL4:0
6:5 PSEL1:0
7 Reserved
8 PLLE
9 PLLC
10 PLOCK
15:11 Reserved
PLL Interrupt
The PLOCK bit in the PLLSTAT register is connected to the interrupt controller. This allows for software to turn on the PLL and
continue with other functions without having to wait for the PLL to achieve lock. When the interrupt occurs (PLOCK = 1), the PLL
may be connected, and the interrupt disabled.
PLL Modes
The combinations of PLLE and PLLC are shown in Table 25.
Table 25: PLL Control Bit Combinations
PLLC PLLE
0 0
0 1
1 0
1 1
PLL Feed Register (PLLFEED - 0xE01FC08C)
A correct feed sequence must be written to the PLLFEED register in order for changes to the PLLCON and PLLCFG registers to
take effect. The feed sequence is:
1. Write the value 0xAA to PLLFEED
2. Write the value 0x55 to PLLFEED.
System Control Block
Read-back for the PLL Multiplier value. This is the value currently used by the PLL.
Read-back for the PLL Divider value. This is the value currently used by the PLL.
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
Read-back for the PLL Enable bit. When one, the PLL is currently activated. When
zero, the PLL is turned off. This bit is automatically cleared when Power Down mode
is activated.
Read-back for the PLL Connect bit. When PLLC and PLLE are both one, the PLL is
connected as the clock source for the LPC2119/2129/2292/2294. When either PLLC
or PLLE is zero, the PLL is bypassed and the oscillator clock is used directly by the
LPC2119/2129/2292/2294. This bit is automatically cleared when Power Down mode
is activated.
Reflects the PLL Lock status. When zero, the PLL is not locked. When one, the PLL
is locked onto the requested frequency.
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
PLL is turned off and disconnected. The system runs from the unmodified clock input.
The PLL is active, but not yet connected. The PLL can be connected after PLOCK is asserted.
Same as 0 0 combination. This prevents the possibility of the PLL being connected without also being
enabled.
The PLL is active and has been connected as the system clock source.
LPC2119/2129/2292/2294
Description
PLL Function
60
Preliminary User Manual
Reset
Value
0
0
NA
0
0
0
NA
January 08, 2004