Figure 14: Pll Block Diagram - Philips LPC2119 User Manual

Philips Semiconductors
ARM-based Microcontroller
PLLC
PLLE
0
PSEL[1:0]
0
F
OSC
PLOCK
MSEL[4:0]
PLL Control Register (PLLCON - 0xE01FC080)
The PLLCON register contains the bits that enable and connect the PLL. Enabling the PLL allows it to attempt to lock to the
current settings of the multiplier and divider values. Connecting the PLL causes the processor and all chip functions to run from
the PLL output clock. Changes to the PLLCON register do not take effect until a correct PLL feed sequence has been given (see
PLL Feed Register (PLLFEED - 0xE01FC08C) description).
System Control Block
Direct
pd
Bypass
Phase-
Frequency
CCO
Detector
cd
fout
Div-by-M
msel<4:0>

Figure 14: PLL Block Diagram

Clock
Synchronization
pd
1
cd
F
CCO
0
/2P
pd
58
Preliminary User Manual
LPC2119/2129/2292/2294
0
0
1
cclk
1
January 08, 2004