External Memory Interface - Philips LPC2119 User Manual

Philips Semiconductors
ARM-based Microcontroller

EXTERNAL MEMORY INTERFACE

External memory interface depends on the bank width (32, 16 or 8 bit selected via MW bits in corresponding BCFG register).
Furthermore, choice of the memory chip(s) will require an adequate setup of RBLE bit in BCFG register, too. RBLE = 0 in case
of 8-bit based external memories, while memory chips capable of accepting 16 or 32 bit wide data will work with RBLE = 1.
If a memory bank is configured to be 32 bits wide, address lines A0 and A1 can be used as non-address lines. Memory bank
configured to 16 bits wide will not require A0, while 8 bit wide memory bank will require address lines down to A0. Configuring
A1 and/or A0 line(s) to provide address or non-address function is acomplished using bits 23 and 24 in Pin Function Select
Register 2 (PINSEL2 register).
Symbol "a_b" in following figures refers to the highest order address line in the data bus. Symbol "a_m" refers to the highest order
address line of the memory chip used in the external memory interface
CS
OE
CE
OE
BLS[3] WE
D[31:24] IO[7:0]
A[a_m:0]
A[a_b:2]
CS
OE
WE
CE
OE
WE
BLS[3]
UB
BLS[2] LB
D[31:16]
IO[15:0]
A[a_m:0]
A[a_b:2]
b) 32 bit wide memory bank interfaced to 16 bit memory chips
External Memory Controller (EMC)
CE
OE
BLS[2] WE
D[23:16] IO[7:0]
A[a_m:0]
a) 32 bit wide memory bank interfaced to 8 bit memory chips
CE
OE
WE
BLS[1]
UB
BLS[0] LB
D[15:0]
IO[15:0]
A[a_m:0]
Figure 7: 32 Bit Bank External Memory Interfaces
LPC2119/2129/2292/2294
CE
OE
BLS[1] WE
D[15:8] IO[7:0]
A[a_m:0]
WE
A[a_b:0]
c) 32 bit wide memory bank interfaced
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Preliminary User Manual
CE
OE
BLS[0] WE
D[7:0] IO[7:0]
A[a_m:0]
CS
OE
CE
OE
WE
BLS[3]
B3
BLS[2]
B2
BLS[1]
B1
BLS[0]
B0
D[31:0]
IO[31:0]
A[a_m:0]
to 32 bit memory chip
January 08, 2004