Register Description - Philips LPC2119 User Manual

Philips Semiconductors
ARM-based Microcontroller

REGISTER DESCRIPTION

Table 74: UART0 Register Map
Address
Name Description
Offset
0xE000C000
U0RBR
DLAB = 0
0xE000C000
U0THR
DLAB = 0
0xE000C004
U0IER
DLAB = 0
Interrupt ID
0xE000C008 U0IIR
0xE000C008 U0FCR
Line Control
0xE000C00C U0LCR
Line Status
0xE000C014 U0LSR
Scratch Pad
0xE000C01C U0SCR
Divisor Latch
0xE000C000
U0DLL
DLAB = 1
Divisor Latch
0xE000C004
U0DLM
DLAB = 1
*Reset Value refers to the data stored in used bits only. It does not include reserved bits content.
UART0 contains ten 8-bit registers as shown in Table 74. The Divisor Latch Access Bit (DLAB) is contained in U0LCR7 and
enables access to the Divisor Latches.
UART0 Receiver Buffer Register (U0RBR - 0xE000C000 when DLAB = 0, Read Only)
The U0RBR is the top byte of the UART0 Rx FIFO. The top byte of the Rx FIFO contains the oldest character received and can
be read via the bus interface. The LSB (bit 0) represents the "oldest" received data bit. If the character received is less than 8
bits, the unused MSBs are padded with zeroes.
The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the U0RBR. The U0RBR is always Read Only.
UART0
BIT 7 BIT 6
Receiver
Buffer MSB
Register
Transmit
Holding MSB
Register
Interrupt
Enable 0 0
Register
FIFOs Enabled
Register
FIFO
Control Rx Trigger
Register
Register
Rx
FIFO TEMT
Register
Error
MSB
Register
MSB
LSB
MSB
MSB
BIT 5 BIT 4 BIT 3
READ DATA
WRITE DATA
0 0 0
0 0 IIR3
Reserved -
THRE BI FE
111
Preliminary User Manual
LPC2119/2129/2292/2294
BIT 2 BIT 1 BIT 0 Access
LSB
LSB
IIR2 IIR1 IIR0
Word Length
Select
PE OE DR
LSB
LSB
LSB
January 08, 2004
Reset
Value*
un-
RO
defined
WO NA
R/W 0
RO 0x01
WO 0
R/W 0
RO 0x60
R/W 0
R/W 0x01
R/W 0