Philips LPC2119 User Manual page 163

Philips Semiconductors
ARM-based Microcontroller
Table 127: CAN Interrupt and Capture Register (CANICR - 0xE00x x00C)
CANICR Name Function
1: Receive Interrupt -- this bit is set whenever the RBS bit in CANSR and the RIE
0 RI
bit in CANIER are both 1, indicating that a received message is available.=.
1: Transmit Interrupt 1 -- this bit is set when the TBS1 bit in CANSR goes from 0
1 TI1
to 1, indicating that Transmit buffer 1 is available, and the TIE1 bit in CANIER is 1.
1: Error Warning Interrupt -- this bit is set on every change (set or clear) of the Error
2 EI Status or Bus Status bit in CANSR, if the EIE bit in CAN is 1 at the time of the
change.
1: Data Overrun Interrupt -- this bit is set when the DOS bit in CANSR goes from
3 DOI
0 to 1, if the DOIE bit in CANIE is 1.
1: Wake-Up Interrupt: this bit is set if the CAN controller is sleeping and bus activity
4 WUI
is detected, if the WUIE bit in CANIE is 1.
1: Error Passive Interrupt -- this bit is set if the EPIE bit in CANIE is 1, and the CAN
5 EPI controller switches between Error Passive and Error Active mode in either
direction.
1: Arbitration Lost Interrupt -- this bit is set if the ALIE bit in CANIE is 1, and the
6 ALI
CAN controller loses arbitration while attempting to transmit.
1: Bus Error Interrupt -- this bit is set if the BEIE bit in CANIE is 1, and the CAN
7 BEI
controller detects an error on the bus.
1: ID Ready Interrupt -- this bit is set if the IDIE bit in CANIE is 1, and a CAN
8 IDI
Identifier has been received.
1: Transmit Interrupt 2 -- this bit is set when the TBS2 bit in CANSR goes from 0
9 TI2
to 1, indicating that Transmit buffer 2 is available, and the TIE2 bit in CANIER is 1.
1: Transmit Interrupt 1 -- this bit is set when the TBS3 bit in CANSR goes from 0
10 TI3
to 1, indicating that Transmit buffer 3 is available, and the TIE3 bit in CANIER is 1.
Error Code Capture: when the CAN controller detects a bus error, the location of
the error within the frame is captured in this field. The value reflects an internal
state variable, and as a result is not very linear:
00011: Start of Frame
00100: SRTR bit
01111: ID12:5
20:16 ERRBIT
01011: DLC
11000: CRC delimiter
11011: End of Frame
10110: Passive error flag 10011: dominant OK bits 10111: Error delimiter
11000: Overload flag
Reading this byte enables another Bus Error Interrupt.
When the CAN controller detects a bus error, the direction of the current bit is
21 ERRDIR
captured in this bit. 1=receiving, 0=transmitting.
When the CAN controller detects a bus error, the type of error is captured in this
23:22 ERRC field:
00=bit error, 01=Form error, 10=Stuff error, 11=other error.
Each time arbitration is lost while trying to send on the CAN, the bit number within
the frame is captured into this field. 0 indicates arbitration loss in the first (MS) bit
28:24 ALCBIT
of the Identifier ... 31 indicates loss in the RTR bit of an extended frame. After this
byte is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur.
CAN Controllers and Acceptance Filter
00010: ID28:21
00101: IDE bit
01110: ID4:0
01010: Data field
11001: Ack slot
10010: Intermission
163
LPC2119/2129/2292/2294
00110: ID20:18
00111: ID17:13
01100: RTR bit
01000: CRC
11011: Ack delimiter
10001: Active Error flag
Preliminary User Manual
Reset Value RM Set
0 0
0 0
0 X
0 0
0 0
0 0
0 0
0 X
0 0
0 0
0 0
0 X
0 X
0 X
0 X
January 08, 2004