Operation - Philips LPC2119 User Manual

Philips Semiconductors
ARM-based Microcontroller
A/D Data Register (ADDR - 0xE0034004)
.
ADDR Name
This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read
31 DONE and when the ADCR is written. If the ADCR is written while a conversion is still in progress,
this bit is set and a new conversion is started.
This bit is 1 in burst mode if the results of one or more conversions was (were) lost and
30 OVERUN overwritten before the conversion that produced the result in the LS bits. In non-FIFO
operation, this bit is cleared by reading this register.
These bits always read as zeroes. They could be used for expansion of the CHN field in
29:27
future compatible A/D converters that can convert more channels.
26:24 CHN These bits contain the channel from which the LS bits were converted.
These bits always read as zeroes. They allow accumulation of successive A/D values without
23:16
AND-masking, for at least 256 values without overflow into the CHN field.
When DONE is 1, this field contains a binary fraction representing the voltage on the Ain pin
selected by the SEL field, divided by the voltage on the VddA pin. Zero in the field indicates
that the voltage on the Ain pin was less than, equal to, or close to that on VssA, while 0x3FF
indicates that the voltage on Ain was close to, equal to, or greater than that on VddA.
15:6 V/VddA
For testing, data written to this field is captured in a shift register that is clocked by the A/D
converter clock. The MS bit of this register sources the DINSERI input of the A/D converter,
which is used only when TEST1:0 are 10.
These bits always read as zeroes. They provide compatible expansion room for future,
5:0
higher-resolution A/D converters.
Table 174: A/D Data Register (ADDR - 0xE0034004)

OPERATION

Hardware-Triggered Conversion
If the BURST bit in the ADCR is 0 and the START field contains 010-111, the A/D converter will start a conversion when a
transition occurs on a selected pin or Timer Match signal . The choices include conversion on a specified edge of any of 4 Match
signals, or conversion on a specified edge of either of 2 Capture/Match pins. The pin state from the selected pad or the selected
Match signal, XORed with ADCR bit 27, is used in the edge detection logic.
Clock Generation
It is highly desirable that the clock divider for the 4.5 MHz conversion clock be held in a Reset state when the A/D converter is
idle, so that the sampling clock can begin immediately when 01 is written to the START field of the ADCR, or the selected edge
occurs on the selected signal. This feature also saves power, particularly if the A/D converter is used infrequently.
Interrupts
An interrupt request is asserted to the Vectored Interrupt Controller (VIC) when the DONE bit is 1. Software can use the Interrupt
Enable bit for the A/D Converter in the VIC to control whether this assertion results in an interrupt. DONE is negated when the
ADDR is read.
Accuracy vs. Digital Receiver
While the A/D converter can be used to measure the voltage on any AIN pin, regardless of the pin's setting in the Pin Select
register (Pin Connect Block on page 100), selecting the AIN function improves the conversion accuracy by disabling the pin's
digital receiver.
A/D Converter
Description
206
Preliminary User Manual
LPC2119/2129/2292/2294
Reset Value
January 08, 2004
0
0
0
X
0
X
0