Table Of Contents - Philips LPC2119 User Manual

Table Of Contents

List Of Tables9
Document Revision History14
Introduction16
Applications17
Architectural Overview18
On-Chip Static Ram19
Block Diagram20
Lpc2119/2129/2292/2294 Registers21
Lpc2119/2129/2292/2294 Memory Addressing32
Figure 3: Peripheral Memory Map33
Figure 4: Ahb Peripheral Map34
Figure 5: Vpb Peripheral Map35
Lpc2119/2129/2292/2294 Memory Re-Mapping And Boot Block36
Figure 6: Map Of Lower Memory Is Showing Re-Mapped And Re-Mappable Areas (128 Kb Flash)38
Prefetch Abort And Data Abort Exceptions39
External Memory Controller (Emc)40
Pin Description41
External Memory Interface43
Figure 8: 16 Bit Bank External Memory Interfaces44
Typical Bus Sequences45
External Memory Selection46
System Control Block48
Register Description49
Crystal Oscillator50
External Interrupt Inputs51
Figure 13: External Interrupt Logic55
Memory Mapping Control56
Pll (Phase Locked Loop)57
Figure 14: Pll Block Diagram58
Power Control63
Reset66
Vpb Divider67
Figure 16: Vpb Divider Connections68
Wakeup Timer69
Memory Accelerator Module (Mam)70
Figure 17: Simplified Block Diagram Of The Memory Accelerator Module71
Memory Accelerator Module Operating Modes72
Mam Configuration73
Mam Usage Notes74
Vectored Interrupt Controller (Vic)76
Vic Registers79
Interrupt Sources83
Figure 18: Block Diagram Of The Vectored Interrupt Controller84
Vic Usage Notes85
Pin Configuration86
Pin Description For Lpc2119/212987
Lpc2292/2294 Pinout91
Pin Description For Lpc2292/229492
Pin Connect Block100
Boot Control On 144-Pin Package105
Gpio106
Gpio Usage Notes109
Uart0110
Architecture119
Figure 21: Uart0 Block Diagram120
Uart1122
Figure 22: Uart1 Block Diagram135
I2C Interface136
Figure 24: Slave Mode Configuration137
Figure 25: Format In The Master Transmitter Mode138
Figure 27: A Master Receiver Switch To Master Transmitter After Sending Repeated Start139
Spi Interface148
Figure 32: Spi Data Transfer Format (Cpha = 0 And Cpha = 1)149
Can Controllers And Acceptance Filter158
Can Controllers159
Can Controller Operation169
Centralized Can Registers171
Figure 34: Entry In Fullcan And Individual Standard Identifier Tables172
Acceptance Filter Registers173
Examples Of Acceptance Filter Tables And Id Index Values175
Fullcan Mode176
Timer0 And Timer1180
Description181
Example Timer Operation187
Pulse Width Modulator (Pwm)190
Figure 41: Pwm Block Diagram192
Figure 42: Sample Pwm Waveforms193
A/D Converter204
Operation206
Real Time Clock208
Rtc Interrupts211
Miscellaneous Register Group212
Consolidated Time Registers215
Time Counter Group217
Alarm Register Group218
Reference Clock Divider (Prescaler)219
Figure 44: Rtc Prescaler Block Diagram220
Watchdog222
Flash Memory System And Programming228
Figure 46: Map Of Lower Memory After Any Reset (128 Kb Flash Part)229
Boot Process Flowchart232
Sector Numbers233
Figure 48: Iap Parameter Passing244
Jtag Flash Programming Interface248
Embeddedice Logic250
Embedded Trace Macrocell254
Realmonitor258
Figure 51: Realmonitor Components259
Figure 52: Realmonitor As A State Machine260
How To Enable Realmonitor262
Figure 53: Exception Handlers263
Realmonitor Build Options268