Can Controller Operation - Philips LPC2119 User Manual

Philips Semiconductors
ARM-based Microcontroller
Tx Data Register A (CANTDA1, 2, 3 - 0xE00x x038, 48, 58)
When the corresponding TBS bit in CANSR is 1, software can write to one of these registers to define the first 1-4 Data bytes of
the next transmit message.
Table 140: CAN Tx Data Register A (CANTDA1, 2, 3 - 0xE00x x038, 48, 58)
CANTDA Name Function
If RTR=0 and DLC >= 0001 in the corresponding CANTFI, this byte is sent as the
7:0 Data 1
first Data byte of the next transmit message.
If RTR=0 and DLC >= 0010 in the corresponding CANTFI, this byte is sent as the
15:8 Data 2
2nd Data byte of the next transmit message.
If RTR=0 and DLC >= 0011 in the corresponding CANTFI, this byte is sent as the
23:16 Data 3
3rd Data byte of the next transmit message.
If RTR=0 and DLC >= 0100 in the corresponding CANTFI, this byte is sent as the
31:24 Data 4
4th Data byte of the next transmit message.
Tx Data Register B (CANTDB1, 2, 3 - 0xE00x x03C, 4C, 5C)
When the corresponding TBS bit in CANSR is 1, software can write to one of these registers to define the 5th through 8th Data
bytes of the next transmit message.
Table 141: CAN Tx Data Register B (CANTDB1, 2, 3 - 0xE00x x03C, 4C, 5C)
CANTDB Name Function
If RTR=0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the
7:0 Data 5
5th Data byte of the next transmit message.
If RTR=0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the
15:8 Data 6
6th Data byte of the next transmit message.
If RTR=0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the
23:16 Data 7
7th Data byte of the next transmit message.
If RTR=0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the
31:24 Data 8
8th Data byte of the next transmit message.

CAN CONTROLLER OPERATION

Error Handling
The CAN Controllers count and handle transmit and receive errors as specified in CAN Spec 2.0B. The Transmit and Receive
Error Counters are incremented for each detected error and are decremented when operation is error-free. If the Transmit Error
counter contains 255 and another error occurs, the CAN Controller is forced into a state called Bus-Off. In this state, the following
register bits are set: BS in CANSR, BEI and EI in CANIR if these are enabled, and RM in CANMOD. RM resets and disables
much of the CAN Controller. Also at this time the Transmit Error Counter is set to 127 and the Receive Error Counter is cleared.
Software must next clear the RM bit. Thereafter the Transmit Error Counter will count down 128 occurrences of the Bus Free
condition (11 consecutive recessive bits). Software can monitor this countdown by reading the Tx Error Counter. When this
countdown is complete, the CAN Controller clears BS and ES in CANSR, and sets EI in CANSR if EIE in IER is 1.
The Tx and Rx error counters can be written if RM in CANMOD is 1. Writing 255 to the Tx Error Counter forces the CAN Controller
to Bus-Off state. If Bus-Off (BS in CANSR) is 1, writing any value 0 through 254 to the Tx Error Counter clears Bus-Off. When
software clears RM in CANMOD thereafter, only one Bus Free condition (11 consecutive recessive bits) is needed before
operation resumes.
CAN Controllers and Acceptance Filter
LPC2119/2129/2292/2294
169
Preliminary User Manual
Reset Value RM Set
0 X
0 X
0 X
0 X
Reset Value RM Set
0 X
0 X
0 X
0 X
January 08, 2004