Architectural Overview - Philips LPC2119 User Manual

Philips Semiconductors Preliminary User Manual
ARM-based Microcontroller LPC2119/2129/2292/2294

ARCHITECTURAL OVERVIEW

The LPC2119/2129/2292/2294 consists of an ARM7TDMI-S CPU with emulation support, the ARM7 Local Bus for interface to
on-chip memory controllers, the AMBA Advanced High-performance Bus (AHB) for interface to the interrupt controller, and the
VLSI Peripheral Bus (VPB, a compatible superset of ARM's AMBA Advanced Peripheral Bus) for connection to on-chip peripheral
functions. The LPC2119/2129/2292/2294 configures the ARM7TDMI-S processor in little-endian byte order.
AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the 4 gigabyte ARM memory space. Each
AHB peripheral is allocated a 16 kilobyte address space within the AHB address space. LPC2119/2129/2292/2294 peripheral
functions (other than the interrupt controller) are connected to the VPB bus. The AHB to VPB bridge interfaces the VPB bus to
the AHB bus. VPB peripherals are also allocated a 2 megabyte range of addresses, beginning at the 3.5 gigabyte address point.
Each VPB peripheral is allocated a 16 kilobyte address space within the VPB address space.
The connection of on-chip peripherals to device pins is controlled by a Pin Connection Block. This must be configured by software
to fit specific application requirements for the use of peripheral functions and pins.
ARM7TDMI-S PROCESSOR
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption.
The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity
results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor
core.
Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically,
while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to
high-volume applications with memory restrictions, or applications where code density is an issue.
The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two
instruction sets:
• The standard 32-bit ARM instruction set.
• A 16-bit THUMB instruction set.
The THUMB set's 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of
the ARM's performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB
code operates on the same 32-bit register set as ARM code.
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM
processor connected to a 16-bit memory system.
The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet that can be found on official ARM website.
ON-CHIP FLASH MEMORY SYSTEM
The LPC2219 incorporate a 128 kB Flash memory system, while LPC2129/2292/2294 incorporate a 256 kB Flash memory
system. This memory may be used for both code and data storage. Programming of the Flash memory may be accomplished in
several ways: over the serial built-in JTAG interface, using In System Programming (ISP) and UART0, or by means of In
Application Programming (IAP) capabilities. The application program, using the In Application Programming (IAP) functions, may
also erase and/or program the Flash while the application is running, allowing a great degree of flexibility for data storage field
firmware upgrades, etc.
Introduction 18 January 08, 2004