Philips LPC2119 User Manual page 164

Philips Semiconductors
ARM-based Microcontroller
Interrupt Enable Register (CANIER - 0xE00x x010)
This read/write register controls whether various events on the CAN controller will result in an interrupt. Bits 7:0 in this register
correspond 1-to-1 with bits 7:0 in the CANICR register.
Table 128: CAN Interrupt Enable Register (CANIER - 0xE00x x010)
CANIER Name Function
0 RIE Receiver Interrupt Enable.
1 TIE1 Transmit Interrupt Enable (1)
2 EIE Error Warning Interrupt Enable
3 DOIE Data Overrun Interrupt Enable
4 WUIE Wake-Up Interrupt Enable
5 EPIE Error Passive Interrupt Enable
6 ALIE Arbitration Lost Interrupt Enable
7 BEIE Bus Error Interrupt Enable
8 IDIE ID Ready Interrupt Enable
9 TIE2 Transmit Interrupt Enable (2)
10 TIE3 Transmit Interrupt Enable (3)
Bus Timing Register (CANBTR - 0xE00x x014)
This register controls how various CAN timings are derived from the VPB clock. It can be read at any time, but can only be written
if the RM bit in CANmod is 1.
Table 129: CAN Bus Timing Register (CANBTR - 0xE00x x014)
CANBTR Name Function
Baud Rate Prescaler. The VPB clock is divided by (this value plus one) to produce
0:9 BRP
the CAN clock.
15:14 SJW The Synchronization Jump Width is (this value plus one) CAN clocks.
The delay from the nominal Sync point to the sample point is (this value plus one)
19:16 TSEG1
CAN clocks.
The delay from the sample point to the next nominal sync point is (this value plus
22:20 TSEG2 one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1
plus 3) CAN clocks.
1: the bus is sampled 3 times (recommended for low to medium speed buses)
23 SAM
0: the bus is sampled once (recommended for high speed buses)
CAN Controllers and Acceptance Filter
LPC2119/2129/2292/2294
164
Preliminary User Manual
Reset Value RM Set
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
0 X
Reset Value RM Set
0 X
0 X
1100 X
001 X
0 X
January 08, 2004