Philips LPC2119 User Manual page 183

Philips Semiconductors
ARM-based Microcontroller
Interrupt Register (IR: TIMER0 - T0IR: 0xE0004000; TIMER1 - T1IR: 0xE0008000)
The Interrupt Register consists of four bits for the match interrupts and four bits for the capture interrupts. If an interrupt is
generated then the corresponding bit in the IR will be high. Otherwise, the bit will be low. Writing a logic one to the corresponding
IR bit will reset the interrupt. Writing a zero has no effect.
Table 157: Interrupt Register (IR: TIMER0 - T0IR: 0xE0004000; TIMER1 - T1IR: 0xE0008000)
IR Function
0 MR0 Interrupt
1 MR1 Interrupt
2 MR2 Interrupt
3 MR3 Interrupt
4 CR0 Interrupt
5 CR1 Interrupt
6 CR2 Interrupt
7 CR3 Interrupt
Timer Control Register (TCR: TIMER0 - T0TCR: 0xE0004004; TIMER1 - T1TCR: 0xE0008004)
The Timer Control Register (TCR) is used to control the operation of the Timer Counter.
Table 158: Timer Control Register (TCR: TIMER0 - T0TCR: 0xE0004004; TIMER1 - T1TCR: 0xE0008004)
TCR Function
0 Counter Enable
1 Counter Reset
Timer Counter (TC: TIMER0 - T0TC: 0xE0004008; TIMER1 - T1TC: 0xE0008008)
The 32-bit Timer Counter is incremented when the Prescale Counter reaches its terminal count. Unless it is reset before reaching
its upper limit, the TC will count up through the value 0xFFFFFFFF and then wrap back to the value 0x00000000. This event
does not cause an interrupt, but a Match register can be used to detect an overflow if needed.
Prescale Register (PR: TIMER0 - T0PR: 0xE000400C; TIMER1 - T1PR: 0xE000800C)
The 32-bit Prescale Register specifies the maximum value for the Prescale Counter.
Timer0 and Timer1
Interrupt flag for match channel 0.
Interrupt flag for match channel 1.
Interrupt flag for match channel 2.
Interrupt flag for match channel 3.
Interrupt flag for capture channel 0 event.
Interrupt flag for capture channel 1 event.
Interrupt flag for capture channel 2 event.
Interrupt flag for capture channel 3 event.
When one, the Timer Counter and Prescale Counter are enabled for counting. When
zero, the counters are disabled.
When one, the Timer Counter and the Prescale Counter are synchronously reset on the
next positive edge of pclk. The counters remain reset until TCR[1] is returned to zero.
LPC2119/2129/2292/2294
Description
Description
183
Preliminary User Manual
Reset
Value
0
0
0
0
0
0
0
0
Reset
Value
0
0
January 08, 2004