Philips LPC2119 User Manual page 199

Philips Semiconductors
ARM-based Microcontroller
PWM Timer Control Register (PWMTCR - 0xE0014004)
The PWM Timer Control Register (PWMTCR) is used to control the operation of the PWM Timer Counter. The function of each
of the bits is shown in Table 167.
Table 167: PWM Timer Control Register (PWMTCR - 0xE0014004)
PWMTCR Function
0 Counter Enable
1 Counter Reset
2 Reserved
3 PWM Enable
PWM Timer Counter (PWMTC - 0xE0014008)
The 32-bit PWM Timer Counter is incremented when the Prescale Counter reaches its terminal count. Unless it is reset before
reaching its upper limit, the PWMTC will count up through the value 0xFFFFFFFF and then wrap back to the value 0x00000000.
This event does not cause an interrupt, but a Match register can be used to detect an overflow if needed.
PWM Prescale Register (PWMPR - 0xE001400C)
The 32-bit PWM Prescale Register specifies the maximum value for the PWM Prescale Counter.
PWM Prescale Counter Register (PWMPC - 0xE0014010)
The 32-bit PWM Prescale Counter controls division of pclk by some constant value before it is applied to the PWM Timer Counter.
This allows control of the relationship of the resolution of the timer versus the maximum time before the timer overflows. The
PWM Prescale Counter is incremented on every pclk. When it reaches the value stored in the PWM Prescale Register, the PWM
Timer Counter is incremented and the PWM Prescale Counter is reset on the next pclk. This causes the PWM TC to increment
on every pclk when PWMPR = 0, every 2 pclks when PWMPR = 1, etc.
PWM Match Registers (PWMMR0 - PWMMR6)
ThePWM Match register values are continuously compared to the PWM Timer Counter value. When the two values are equal,
actions can be triggered automatically. The action possibilities are to generate an interrupt, reset the PWM Timer Counter, or
stop the timer. Actions are controlled by the settings in the PWMMCR register.
Pulse Width Modulator (PWM)
When one, the PWM Timer Counter and PWM Prescale Counter are enabled for
counting. When zero, the counters are disabled.
When one, the PWM Timer Counter and the PWM Prescale Counter are
synchronously reset on the next positive edge of pclk. The counters remain reset until
TCR[1] is returned to zero.
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
When one, PWM mode is enabled. PWM mode causes shadow registers to operate
in connection with the Match registers. A program write to a Match register will not
have an effect on the Match result until the corresponding bit in PWMLER has been
set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match
register that determines the PWM rate (PWM Match 0) must be set up prior to the
PWM being enabled. Otherwise a Match event will not occur to cause shadow register
contents to become effective.
LPC2119/2129/2292/2294
Description
199
Preliminary User Manual
Reset
Value
0
0
NA
0
January 08, 2004