Chapter 5: Vectored Interrupt Controller (Vic); Features; Description; Register Description - Philips LPC2101 User Manual

5.1 Features

5.2 Description

The Vectored Interrupt Controller (VIC) takes 32 interrupt request inputs and
programmably assigns them into 3 categories, FIQ, vectored IRQ, and non-vectored IRQ.
The programmable assignment scheme means that priorities of interrupts from the
various peripherals can be dynamically assigned and adjusted.
Fast Interrupt reQuest (FIQ) requests have the highest priority. If more than one request is
assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM
processor. The fastest possible FIQ latency is achieved when only one request is
classified as FIQ because then the FIQ service routine can simply start dealing with that
device. But if more than one request is assigned to the FIQ class, the FIQ service routine
can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an
interrupt.
Vectored IRQs have the middle priority, but only 16 of the 32 requests can be assigned to
this category. Any of the 32 requests can be assigned to any of the 16 vectored IRQ slots
among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority.
The VIC ORs the requests from all the vectored and non-vectored IRQs to produce the
IRQ signal to the ARM processor. The IRQ service routine can start by reading a register
from the VIC and jumping there. If any of the vectored IRQs are requesting, the VIC
provides the address of the highest-priority requesting IRQs service routine, otherwise it
provides the address of a default routine that is shared by all the non-vectored IRQs. The
default routine can read another VIC register to see what IRQs are active.
All registers in the VIC are word registers. Byte and halfword reads and write are not
supported.
Additional information on the Vectored Interrupt Controller is available in the ARM
PrimeCell™ Vectored Interrupt Controller (PL190) documentation.

5.3 Register description

The VIC implements the registers shown in
User manual
UM10161

Chapter 5: Vectored Interrupt Controller (VIC)

Rev. 01 — 12 January 2006
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ARM PrimeCell™ Vectored Interrupt Controller
•
32 interrupt request inputs
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16 vectored IRQ interrupts
•
16 priority levels dynamically assigned to interrupt requests
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Software interrupt generation
Rev. 01 — 12 January 2006
User manual
Table 35. More detailed descriptions follow.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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