Pll Configuration Register (Pllcfg - 0Xe01F C084); Pll Status Register (Pllstat - 0Xe01F C088) - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
Table 16:
Bit
0
1
7:2
The PLL must be set up, enabled, and Lock established before it may be used as a clock
source. When switching from the oscillator clock to the PLL output or vice versa, internal
circuitry synchronizes the operation in order to ensure that glitches are not generated.
Hardware does not insure that the PLL is locked before it is connected or automatically
disconnect the PLL if lock is lost during operation. In the event of loss of PLL lock, it is
likely that the oscillator clock has become unstable and disconnecting the PLL will not
remedy the situation.

3.8.3 PLL Configuration register (PLLCFG - 0xE01F C084)

The PLLCFG register contains the PLL multiplier and divider values. Changes to the
PLLCFG register do not take effect until a correct PLL feed sequence has been given (see
Section 3.8.7 "PLL Feed register (PLLFEED - 0xE01F C08C)" on page
for the PLL frequency, and multiplier and divider values are found in the PLL Frequency
Calculation section on
Table 17:
Bit
4:0
6:5
7

3.8.4 PLL Status register (PLLSTAT - 0xE01F C088)

The read-only PLLSTAT register provides the actual PLL parameters that are in effect at
the time it is read, as well as the PLL status. PLLSTAT may disagree with values found in
PLLCON and PLLCFG because changes to those registers do not take effect until a
proper PLL feed has occurred (see
0xE01F
User manual
PLL Control register (PLLCON - address 0xE01F C080) bit description
Symbol Description
PLLE PLL Enable. When one, and after a valid PLL feed, this bit will
activate the PLL and allow it to lock to the requested frequency. See
PLLSTAT register,
PLLC PLL Connect. When PLLC and PLLE are both set to one, and after a
valid PLL feed, connects the PLL as the clock source for the
microcontroller. Otherwise, the oscillator clock is used directly by the
microcontroller. See PLLSTAT register,
- Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Section 3.8.9 "PLL frequency calculation" on page
PLL Configuration register (PLLCFG - address 0xE01F C084) bit description
Symbol Description
MSEL PLL Multiplier value. Supplies the value "M" in the PLL frequency
calculations.
Note: For details on selecting the right value for MSEL see
3.8.9 "PLL frequency calculation" on page
PSEL PLL Divider value. Supplies the value "P" in the PLL frequency
calculations.
Note: For details on selecting the right value for PSEL see
3.8.9 "PLL frequency calculation" on page
- Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
C08C)").
Rev. 01 — 12 January 2006
Chapter 3: System control block
Table 18.
Table
29.
29.
Section 3.8.7 "PLL Feed register (PLLFEED -
UM10161
Reset
value
0
0
18.
NA
29). Calculations
29.
Reset
value
0
Section
0
Section
NA
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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