Uart0 Receiver Buffer Register (U0Rbr - 0Xe000 C000, When Dlab = 0, Read Only); Uart0 Transmit Holding Register (U0Thr - 0Xe000 C000, When Dlab = 0, Write Only); Uart0 Divisor Latch Registers (U0Dll - 0Xe000 C000 And U0Dlm - 0Xe000 C004, When Dlab = 1); User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
9.3.1 UART0 Receiver Buffer register (U0RBR - 0xE000 C000, when
DLAB = 0, Read Only)
The U0RBR is the top byte of the UART0 Rx FIFO. The top byte of the Rx FIFO contains
the oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the "oldest" received data bit. If the character received is less than 8 bits, the
unused MSBs are padded with zeroes.
The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the
U0RBR. The U0RBR is always Read Only.
Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e.
the one that will be read in the next read from the RBR), the right approach for fetching the
valid pair of received byte and its status bits is first to read the content of the U0LSR
register, and then to read a byte from the U0RBR.
Table 82:
Bit
7:0
9.3.2 UART0 Transmit Holding Register (U0THR - 0xE000 C000, when
DLAB = 0, Write Only)
The U0THR is the top byte of the UART0 TX FIFO. The top byte is the newest character in
the TX FIFO and can be written via the bus interface. The LSB represents the first bit to
transmit.
The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the
U0THR. The U0THR is always Write Only.
Table 83:
Bit
7:0
9.3.3 UART0 Divisor Latch registers (U0DLL - 0xE000 C000 and U0DLM -
0xE000 C004, when DLAB = 1)
The UART0 Divisor Latch is part of the UART0 Fractional Baud Rate Generator and holds
the value used to divide the clock supplied by the fractional prescaler in order to produce
the baud rate clock, which must be 16x the desired baud rate
and U0DLM registers together form a 16 bit divisor where U0DLL contains the lower 8 bits
of the divisor and U0DLM contains the higher 8 bits of the divisor. A 0x0000 value is
treated like a 0x0001 value as division by zero is not allowed.The Divisor Latch Access Bit
(DLAB) in U0LCR must be one in order to access the UART0 Divisor Latches.
Details on how to select the right value for U0DLL and U0DLM can be found later on in
this chapter.

User manual

UART0 Receiver Buffer Register (U0RBR - address 0xE000 C000, when DLAB = 0,
Read Only) bit description
Symbol Description
RBR The UART0 Receiver Buffer Register contains the oldest
received byte in the UART0 Rx FIFO.
UART0 Transmit Holding Register (U0THR - address 0xE000 C000, when
DLAB = 0, Write Only) bit description
Symbol Description
THR Writing to the UART0 Transmit Holding Register causes the data
to be stored in the UART0 transmit FIFO. The byte will be sent
when it reaches the bottom of the FIFO and the transmitter is
available.
Rev. 01 — 12 January 2006
UM10161
Chapter 9: UART0
Reset value
undefined
Reset value
NA
(Equation 1). The U0DLL
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
84