Control Register, I2Conset And I2Conclr; Status Decoder And Status Register; Register Description; User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1

11.6.8 Control register, I2CONSET and I2CONCLR

The I
and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition,
and acknowledgment.
The contents of the I
will set bits in the I
Conversely, writing to I2CONCLR will clear bits in the I
to ones in the value written.

11.6.9 Status decoder and status register

The status decoder takes all of the internal status bits and compresses them into a 5-bit
code. This code is unique for each I
generate vector addresses for fast processing of the various service routines. Each
service routine processes a particular bus status. There are 26 possible bus states if all
four modes of the I
significant bits of the status register when the serial interrupt flag is set (by hardware) and
remains stable until the interrupt flag is cleared by software. The three least significant bits
of the status register are always zero. If the status code is used as a vector to service
routines, then the routines are displaced by eight address locations. Eight bytes of code is
sufficient for most of the service routines (see the software example in this section).

11.7 Register description

Each I
2
Table 120: I C register map
Name Description
2
I2CONSET I C Control Set Register. When a one is written to a bit
of this register, the corresponding bit in the I
register is set. Writing a zero has no effect on the
corresponding bit in the I
2
I2STAT I C Status Register. During I
provides detailed status codes that allow software to
determine the next action needed.
2
I2DAT I C Data Register. During master or slave transmit mode,
data to be transmitted is written to this register. During
master or slave receive mode, data that has been
received may be read from this register.
2
I2ADR I C Slave Address Register. Contains the 7-bit slave
address for operation of the I
and is not used in master mode. The least significant bit
determines whether a slave responds to the general call
address.

User manual

2
C control register contains bits used to control the following I
2
C control register may be read as I2CONSET. Writing to I2CONSET
2
C control register that correspond to ones in the value written.
2
C block are used. The 5-bit status code is latched into the five most
2
C interface contains 7 registers as shown in
2
C control register.
2
C operation, this register
2
C interface in slave mode,
Rev. 01 — 12 January 2006
2
C-bus status. The 5-bit code may be used to
Table 120
Access Reset
value
R/W 0x00
2
C control
RO 0xF8
R/W 0x00
R/W 0x00
UM10161
2
Chapter 11: I C interfaces
2
C block functions: start
2
C control register that correspond
below.
2 2
I C0 Address I C1 Address
[1]
and Name and Name
0xE001 C000 0xE005 C000
I2C0CONSET I2C1CONSET
0xE001 C004 0xE005 C004
I2C0STAT I2C1STAT
0xE001 C008 0xE005 C008
I2C0DAT I2C1DAT
0xE001 C00C 0xE005 C00C
I2C0ADR I2C1ADR
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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