Mam Timing Register (Mamtim - 0Xe01F C004); Mam Usage Notes - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
Table 33:
Bit
1:0
7:2

4.8 MAM Timing register (MAMTIM - 0xE01F C004)

The MAM Timing register determines how many CCLK cycles are used to access the
Flash memory. This allows tuning MAM timing to match the processor operating
frequency. Flash access times from 1 clock to 7 clocks are possible. Single clock Flash
accesses would essentially remove the MAM from timing calculations. In this case the
MAM mode may be selected to optimize power usage.
Table 34:
Bit
2:0
7:3

4.9 MAM usage notes

When changing MAM timing, the MAM must first be turned off by writing a zero to
MAMCR. A new value may then be written to MAMTIM. Finally, the MAM may be turned
on again by writing a value (1 or 2) corresponding to the desired operating mode to
MAMCR.
For system clock slower than 20 MHz, MAMTIM can be 001. For system clock between
20 MHz and 40 MHz, Flash access time is suggested to be 2 CCLKs, while in systems
with system clock faster than 40 MHz, 3 CCLKs are proposed.
User manual
MAM Control Register (MAMCR - address 0xE01F C000) bit description
Symbol Value Description
MAM_mode 00 MAM functions disabled
_control
01 MAM functions partially enabled
10 MAM functions fully enabled
11 Reserved. Not to be used in the application.
- - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
MAM Timing register (MAMTIM - address 0xE01F C004) bit description
Symbol Value Description
MAM_fetch_ 000 0 - Reserved.
cycle_timing
001 1 - MAM fetch cycles are 1 processor clock (CCLK) in
duration
010 2 - MAM fetch cycles are 2 CCLKs in duration
011 3 - MAM fetch cycles are 3 CCLKs in duration
100 4 - MAM fetch cycles are 4 CCLKs in duration
101 5 - MAM fetch cycles are 5 CCLKs in duration
110 6 - MAM fetch cycles are 6 CCLKs in duration
111 7 - MAM fetch cycles are 7 CCLKs in duration
Warning: These bits set the duration of MAM Flash fetch operations
as listed here. Improper setting of this value may result in incorrect
operation of the device.
- - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 01 — 12 January 2006
UM10161
Chapter 4: MAM Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Reset
value
0
NA
Reset
value
07
NA
43