Example Timer Operation; User Manual - Philips LPC2101 User Manual

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Note: When the match outputs are selected to perform as PWM outputs, the timer reset
(MRnR) and timer stop (MRnS) bits in the Match Control Register MCR must be set to
zero except for the match register setting the PWM cycle length. For this register, set the
MRnR bit to one to enable the timer reset when the timer value matches the value of the
corresponding match register.

16.8 Example timer operation

Figure 54
The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle
where the match occurs, the timer count is reset. This gives a full length cycle to the
match value. The interrupt indicating that a match occurred is generated in the next clock
after the timer reached the match value.
Figure 55
prescaler is again set to 2 and the match register set to 6. In the next clock after the timer
reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.
PCLK
prescale
counter
timer
counter
timer counter
reset
interrupt
Fig 54. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled

User manual

PWM2/MAT2
PWM1/MAT1
PWM0/MAT0
Fig 53. Sample PWM waveforms with a PWM cycle length of 100 (selected by MR3) and
MAT3:0 enabled as PWM outputs by the PWCON register.
shows a timer configured to reset the count and generate an interrupt on match.
shows a timer configured to stop and generate an interrupt on match. The
2 0 1 2
4 5
Rev. 01 — 12 January 2006
0 41
0 1 2 0
6
UM10161
Chapter 16: Timer2 and Timer3
MR2 = 100
MR1 = 41
MR0 = 65
65 100
(counter is reset)
1 2 0 1
0 1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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