C-Bus Obstructed By A Low Level On Scl Or Sda; Bus Error; User Manual - Philips LPC2101 User Manual

Philips Semiconductors
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If an uncontrolled source generates a superfluous START or masks a STOP condition,
then the I
obtained within a reasonable amount of time, then a forced access to the I
possible. This is achieved by setting the STO flag while the STA flag is still set. No STOP
condition is transmitted. The I
and is able to transmit a START condition. The STO flag is cleared by hardware (see
Figure 34).
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11.8.12 I
An I
SCL line is obstructed (pulled LOW) by a device on the bus, no further serial transfer is
possible, and the I
problem must be resolved by the device that is pulling the SCL bus line LOW.
If the SDA line is obstructed by another device on the bus (e.g., a slave device out of bit
synchronization), the problem can be solved by transmitting additional clock pulses on the
SCL line (see
STA flag is set, but no START condition can be generated because the SDA line is pulled
LOW while the I
START condition after every two additional clock pulses on the SCL line. When the SDA
line is eventually released, a normal START condition is transmitted, state 0x08 is entered,
and the serial transfer continues.
If a forced bus access occurs or a repeated START condition is transmitted while SDA is
obstructed (pulled LOW), the I
In each case, state 0x08 is entered after a successful START condition is transmitted and
normal serial transfer continues. Note that the CPU is not involved in solving these bus
hang-up problems.

11.8.13 Bus error

A bus error occurs when a START or STOP condition is present at an illegal position in the
format frame. Examples of illegal positions are during the serial transfer of an address
byte, a data bit, or an acknowledge bit.
The I
a master or an addressed slave. When a bus error is detected, the I
switches to the not addressed slave mode, releases the SDA and SCL lines, sets the
interrupt flag, and loads the status register with 0x00. This status code may be used to
vector to a state service routine which either attempts the aborted serial transfer again or
simply recovers from the error condition as shown in

User manual

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C-bus stays busy indefinitely. If the STA flag is set and bus access is not

C-bus obstructed by a LOW level on SCL or SDA

2
C-bus hang-up occurs if SDA or SCL is pulled LOW by an uncontrolled source. If the
2
C hardware cannot resolve this type of problem. When this occurs, the
Figure 38). The I
2
C-bus is considered free. The I
2
C hardware only reacts to a bus error when it is involved in a serial transfer either as
S SLA W A
08H 18H
Fig 36. Simultaneous repeated START conditions from two masters
Rev. 01 — 12 January 2006
2
C hardware behaves as if a STOP condition was received
2
C hardware transmits additional clock pulses when the
2
C hardware attempts to generate a
2
C hardware performs the same action as described above.
OTHER MASTER
DATA A S
28H
other Master sends
repeated START earlier
UM10161
Chapter 11: I
2
C block immediately
Table 137.
P S
CONTINUES
08H
retry
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
2
C interfaces
2
C-bus is
SLA
147