Philips LPC2101 User Manual page 54

Philips Semiconductors
Volume 1
Table 57: Connection of interrupt sources to the Vectored Interrupt Controller (VIC)
Block Flag(s)
I- Reserved
TIMER2 Match 0 - 2 (MR0, MR1, MR2)
Capture 0 - 2 (CR0, CR1, CR2)
TIMER3 Match 0 - 3 (MR0, MR1, MR2, MR3)
interrupt request, masking and selection
SOFTINTCLEAR
SOFTINT
VICINT
SOURCE
[31:0]
RAWINTERRUPT
[31:0]
vector interrupt 0
SOURCE ENABLE
VECTORCNTL[5:0]
vector interrupt 1
vector interrupt 15
Fig 13. Block diagram of the Vectored Interrupt Controller (VIC)
User manual
INTENABLECLEAR
[31:0] [31:0]
INTENABLE
[31:0] [31:0]
INTSELECT
[31:0]
priority 0
VECTIRQ0
VECTADDR0[31:0]
VECTORADDR
[31:0]
priority1
VECTIRQ1
VECTADDR1[31:0]
priority2
priority14
VECTIRQ15
VECTADDR15[31:0]
priority15
Rev. 01 — 12 January 2006
non-vectored FIQ interrupt logic
nVICFIQIN
FIQSTATUS[31:0]
FIQSTATUS
[31:0]
non-vectored IRQ interrupt logic
IRQSTATUS[31:0]
IRQSTATUS
[31:0]
interrupt priority logic
HARDWARE
PRIORITY
LOGIC
DEFAULT
VECTORADDR
[31:0]
nVICIRQIN VICVECTADDRIN[31:0]
UM10161
Chapter 5: VIC
VIC Channel # and Hex
Mask
20- 0x0010 0000
25 0x0200 0000
26 0x0400 0000
27 0x0800 0000
nVICFIQ
NonVectIRQ
IRQ
IRQ
nVICIRQ
address select
for
highest priority
interrupt
VICVECT
VECTORADDR
ADDROUT
[31:0]
[31:0]
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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