Details Of I C Operating Modes; User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
The values for I2SCLL and I2SCLH should not necessarily be the same. Software can set
different duty cycles on SCL by setting these two registers. For example, the I
specification defines the SCL low time and high time at different values for a 400 kHz I
rate. The value of the register must ensure that the data rate is in the I
of 0 through 400 kHz. Each register value must be greater than or equal to 4.
gives some examples of I
I2SCLH values.
Table 128: Example I
I2SCLL +
I2SCLH
8
10
25
50
100
160
200
400
800
2
11.8 Details of I
The four operating modes are:
Data transfers in each mode of operation are shown in
Figure
describing the I
Table 129: Abbreviations used to describe an I
Abbreviation
S
SLA
R
W

User manual

2
C clock rates
1 5
125
100
40 200
20 100
10 50
6.25 31.25
5 25
2.5 12.5
1.25 6.25
C operating modes
•
Master Transmitter
•
Master Receiver
•
Slave Receiver
•
Slave Transmitter
35, and Figure 36.
2
C operating modes.
Explanation
Start Condition
7-bit slave address
Read bit (HIGH level at SDA)
Write bit (LOW level at SDA)
Rev. 01 — 12 January 2006
I 2 C
= -------------------------------------------------------- -
bitfrequency
I2CSCLH
2
C-bus rates based on PCLK frequency and I2SCLL and
2
I C Bit Frequency (kHz) at PCLK (MHz)
10 16
400
200 320
100 160
62.5 100
50 80
25 40
12.5 20
Table 129 lists abbreviations used in these figures when
2
C operation
UM10161
Chapter 11: I
PCLK
+ I2CSCLL
2
C data rate range
20 40
400
200 400
125 250
100 200
50 100
25 50
Figure 32, Figure 33,
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
2
C interfaces
(7)
2
C-bus
2
C
Table 128
60
375
300
150
75
Figure 34,
132