Table of Contents
Advertisement
Philips Semiconductors
Volume 1
Table 162: A/D Status Register (ADSTAT, ADC0: AD0STAT - address 0xE003 4004 ) bit description
Bit
Symbol
Value
2
ADINTEN2
0
1
3
ADINTEN3
0
1
4
ADINTEN4
0
1
5
ADINTEN5
0
1
6
ADINTEN6
0
1
7
ADINTEN1
0
1
8
ADGINTEN
0
1
31:9
-
14.4.5 A/D Data Registers (ADDR0 to ADDR7, ADC0: AD0DR0 to AD0DR7 -
0xE003 4010 to 0xE003 402C)
The A/D Data Register hold the result when an A/D conversion is complete, and also
include the flags that indicate when a conversion has been completed and when a
conversion overrun has occurred.
Table 163: A/D Data Registers (ADDR0 to ADDR7, ADC0: AD0DR0 to AD0DR7) bit description
Bit
Symbol
Description
5:0
-
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
15:6
RESULT
When DONE is 1, this field contains a binary fraction representing the voltage on the AD0 pin,
divided by the voltage on the V
the AD0 pin was less than, equal to, or close to that on V
voltage on AD0 was close to, equal to, or greater than that on V
29:16
-
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
30
OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and
overwritten before the conversion that produced the result in the RESULT bits.This bit is
cleared by reading this register.
31
DONE
This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. NA
User manual
Description
Completion of a conversion on ADC channel 2 will not generate an interrupt.
Completion of a conversion on ADC channel 2 will generate an interrupt.
Completion of a conversion on ADC channel 3 will not generate an interrupt.
Completion of a conversion on ADC channel 3 will generate an interrupt.
Completion of a conversion on ADC channel 4 will not generate an interrupt.
Completion of a conversion on ADC channel 4 will generate an interrupt.
Completion of a conversion on ADC channel 5 will not generate an interrupt.
Completion of a conversion on ADC channel 5 will generate an interrupt.
Completion of a conversion on ADC channel 6 will not generate an interrupt.
Completion of a conversion on ADC channel 6 will generate an interrupt.
Completion of a conversion on ADC channel 7 will not generate an interrupt.
Completion of a conversion on ADC channel 7 will generate an interrupt.
Only the individual ADC channels enabled by ADINTEN7:0 will generate
interrupts.
Only the global DONE flag in ADDR is enabled to generate an interrupt.
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
pin (V/V
REF
Rev. 01 — 12 January 2006
). Zero in the field indicates that the voltage on
REF
, while 0x3FF indicates that the
SSA
.
REF
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
UM10161
Chapter 14: A/D converter
Reset
value
0
0
0
0
0
0
1
NA
Reset
value
NA
NA
NA
185
Advertisement
Chapters
Table of Contents
