I 2 C Control Clear Register; (I2Stat: 2 C Status Register; User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
2
11.7.2 I
0xE001 C018 and I2C1, I2C1CONCLR - 0xE005 C018)
The I2CONCLR registers control clearing of bits in the I2CON register that controls
operation of the I
corresponding bit in the I
Table 122: I
Bit Symbol
1:0 -
2
3
4
5
6
7
AAC is the Assert Acknowledge Clear bit. Writing a 1 to this bit clears the AA bit in the
I2CONSET register. Writing 0 has no effect.
SIC is the I
register. Writing 0 has no effect.
STAC is the Start flag Clear bit. Writing a 1 to this bit clears the STA bit in the I2CONSET
register. Writing 0 has no effect.
I2ENC is the I
I2CONSET register. Writing 0 has no effect.
2
11.7.3 I
I2C1STAT - 0xE005 C004)
Each I
Status register is Read-Only.
Table 123: I
Bit Symbol
2:0 -
7:3 Status
The three least significant bits are always 0. Taken as a byte, the status register contents
represent a status code. There are 26 possible status codes. When the status code is
0xF8, there is no relevant information available and the SI bit is not set. All other 25 status
codes correspond to defined I
be set. For a complete list of status codes, refer to tables from

User manual

C Control Clear register (I2CONCLR: I2C0, I2C0CONCLR -
2
C interface. Writing a one to a bit of this register causes the
2
2
C Control Set register (I2CONCLR: I2C0, I2C0CONCLR - address 0xE001 C018
and I2C1, I2C1CONCLR - address 0xE005 C018) bit description
Description
Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
AAC Assert acknowledge Clear bit.
2
SIC I C interrupt Clear bit.
- Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
STAC START flag Clear bit.
2
I2ENC I C interface Disable bit.
- Reserved. User software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
2
C Interrupt Clear bit. Writing a 1 to this bit clears the SI bit in the I2CONSET
2
C Interface Disable bit. Writing a 1 to this bit clears the I2EN bit in the
C Status register (I2STAT: I2C0, I2C0STAT - 0xE001 C004 and I2C1,
2
C Status register reflects the condition of the corresponding I
2
C Status register (I2STAT: I2C0, I2C0STAT - address 0xE001 C004 and I2C1,
I2C1STAT - address 0xE005 C004) bit description
Description
These bits are unused and are always 0.
These bits give the actual status information about the I
Rev. 01 — 12 January 2006
C control register to be cleared. Writing a zero has no effect.
2
C states. When any of these states entered, the SI bit will
UM10161
2
Chapter 11: I C interfaces
Reset
value
NA
0
NA
0
0
NA
2
C interface. The I
Reset value
0
2
C interface. 0x1F
Table 133 to Table 136.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
2
C
130