User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
When STA is 1 and the I
checks the bus and generates a START condition if the bus is free. If the bus is not free, it
waits for a STOP condition (which will free the bus) and generates a START condition after
a delay of a half clock period of the internal clock generator. If the I
in master mode and data has been transmitted or received, it transmits a repeated START
condition. STA may be set at any time, including when the I
slave mode.
STA can be cleared by writing 1 to the STAC bit in the I2CONCLR register. When STA is 0,
no START condition or repeated START condition will be generated.
If STA and STO are both set, then a STOP condition is transmitted on the I
interface is in master mode, and transmits a START condition thereafter. If the I
interface is in slave mode, an internal STOP condition is generated, but is not transmitted
on the bus.
STO is the STOP flag. Setting this bit causes the I
condition in master mode, or recover from an error condition in slave mode. When STO is
1 in master mode, a STOP condition is transmitted on the I
the STOP condition, STO is cleared automatically.
In slave mode, setting this bit can recover from an error condition. In this case, no STOP
condition is transmitted to the bus. The hardware behaves as if a STOP condition has
been received and it switches to "not addressed" slave receiver mode. The STO flag is
cleared by hardware automatically.
SI is the I
state F8 does not set SI since there is nothing for an interrupt service routine to do in that
case.
While SI is set, the low period of the serial clock on the SCL line is stretched, and the
serial transfer is suspended. When SCL is HIGH, it is unaffected by the state of the SI flag.
SI must be reset by software, by writing a 1 to the SIC bit in I2CONCLR register.
AA is the Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA) will
be returned during the acknowledge clock pulse on the SCL line on the following
situations:
The AA bit can be cleared by writing 1 to the AAC bit in the I2CONCLR register. When AA
is 0, a not acknowledge (HIGH level to SDA) will be returned during the acknowledge
clock pulse on the SCL line on the following situations:

User manual

2
2
C Interrupt Flag. This bit is set when the I
1. The address in the Slave Address Register has been received.
2. The general call address has been received while the general call bit (GC) in I2ADR is
set.
3. A data byte has been received while the I
4. A data byte has been received while the I
1. A data byte has been received while the I
2. A data byte has been received while the I
Rev. 01 — 12 January 2006
C interface is not already in master mode, it enters master mode,
2
C is in the master receiver mode.
2
C is in the addressed slave receiver mode
2
C is in the master receiver mode.
2
C is in the addressed slave receiver mode.
UM10161
Chapter 11: I
2
C interface is already
2
C interface is in an addressed
2
C interface to transmit a STOP
2
C-bus. When the bus detects
2
C state changes. However, entering
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
2
C interfaces
2
C-bus if it the
2
C
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