Setup And Hold Time Requirements On Cs With Respect To Sk In Microwire Mode; Register Description; User Manual - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
13.3.9 Setup and hold time requirements on CS with respect to SK in
Microwire mode
In the Microwire mode, the SSP slave samples the first bit of receive data on the rising
edge of SK after CS has gone LOW. Masters that drive a free-running SK must ensure
that the CS signal has sufficient setup and hold margins with respect to the rising edge of
SK.
Figure 48
edge on which the first bit of receive data is to be sampled by the SSP slave, CS must
have a setup of at least two times the period of SK on which the SSP operates. With
respect to the SK rising edge previous to this edge, CS must have a hold of at least one
SK period.

13.4 Register description

The SSP contains 9 registers as shown in
word accessible.

User manual

SK
CS
SO
LSB
SI
0 MSB
output data
Fig 47. Microwire frame format (continuos transfers)
illustrates these setup and hold time requirements. With respect to the SK rising
SK
CS
SI
Fig 48. Microwire frame format (continuos transfers) - details
Rev. 01 — 12 January 2006
MSB
8 bit control
LSB
4 to 16 bits
t = t
HOLD SK
Table 147. All registers are byte, half word and
UM10161
Chapter 13: SSP
LSB
MSB
4 to 16 bits
output data
t =2*t
SETUP SK
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
LSB
174