Gpio Port 0 Direction Register (Iodir, Port 0: Io0Dir - 0Xe002 8008; Fiodir, Port 0: Fio0Dir - 0X3Fff C000); Koninklijke Philips Electronics N.v. 2006. All Rights Reserved - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
Table 65:
Generic
Name
FIODIR
FIOMASK
FIOPIN
FIOSET
FIOCLR
[1]
8.4.1 GPIO port 0 Direction register (IODIR, Port 0: IO0DIR - 0xE002 8008;
FIODIR, Port 0: FIO0DIR - 0x3FFF C000)
This word accessible register is used to control the direction of the pins when they are
configured as GPIO port pins. Direction bit for any pin must be set according to the pin
functionality.
IO0DIR is the legacy register while the enhanced GPIO functions are supported via the
FIO0DIR register.
Table 66: GPIO port 0 Direction register (IO0DIR - address 0xE002 8008) bit description
Bit Symbol Value Description
31:0 P0xDIR
0
1
User manual
GPIO register map (local bus accessible registers - enhanced GPIO features)
Description
Fast GPIO Port Direction control register.
This register individually controls the
direction of each port pin.
Fast Mask register for port. Writes, sets,
clears, and reads to port (done via writes
to FIOPIN, FIOSET, and FIOCLR, and
reads of FIOPIN) alter or return only the
bits enabled by zeros in this register.
Fast GPIO Port Pin value register using
FIOMASK. The current state of digital port
pins can be read from this register,
regardless of pin direction or alternate
function selection (as long as pins is not
configured as an input to ADC). The value
read is masked by ANDing with
FIOMASK. Writing to this register places
corresponding values in all bits enabled by
ones in FIOMASK.
Fast GPIO Port Output Set register using
FIOMASK. This register controls the state
of output pins. Writing 1s produces HIGH
at the corresponding port pins. Writing 0s
has no effect. Reading this register returns
the current contents of the port output
register. Only bits enabled by ones in
FIOMASK can be altered.
Fast GPIO Port Output Clear register
using FIOMASK. This register controls the
state of output pins. Writing 1s produces
LOW at the corresponding port pins.
Writing 0s has no effect. Only bits enabled
by ones in FIOMASK can be altered.
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Slow GPIO Direction control bits. Bit 0 controls P0.0 ... bit 30 controls P0.30.
Controlled pin is input.
Controlled pin is output.
Rev. 01 — 12 January 2006
UM10161
Chapter 8: GPIO
[1]
Acces Reset value PORT0
s Address &
Name
R/W 0x0000 0000 0x3FFF C000
FIO0DIR
R/W 0x0000 0000 0x3FFF C010
FIO0MASK
R/W 0x0000 0000 0x3FFF C014
FIO0PIN
R/W 0x0000 0000 0x3FFF C018
FIO0SET
WO 0x0000 0000 0x3FFF C01C
FIO0CLR
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Reset value
0x0000 0000
73