Philips LPC2101 User Manual page 14

Philips Semiconductors
Volume 1
For these areas, both attempted data access and instruction fetch generate an exception.
In addition, a Prefetch Abort exception is generated for any instruction fetch that maps to
an AHB or APB peripheral address.
Within the address space of an existing APB peripheral, a data abort exception is not
generated in response to an access to an undefined address. Address decoding within
each peripheral is limited to that needed to distinguish defined registers within the
peripheral itself. For example, an access to address 0xE000 D000 (an undefined address
within the UART0 space) may result in an access to the register defined at address
0xE000 C000. Details of such address aliasing within a peripheral space are not defined
in the LPC2101/02/03 documentation and are not a supported feature.
Note that the ARM core stores the Prefetch Abort flag along with the associated
instruction (which will be meaningless) in the pipeline and processes the abort only if an
attempt is made to execute the instruction fetched from the illegal address. This prevents
accidental aborts that could be caused by prefetches that occur when code is executed
very close to a memory boundary.
User manual
– Address space between on-chip Static RAM and the Boot Block. Labelled
"Reserved Address Space" in
address range from 0x4000 2000 to 0x7FFF DFFF, for 4 kB SRAM device this is
memory address range from 0x4000 1000 to 0x7FFF DFFF, and for 2 kB SRAM
device this range is from 0x4000 0800 to 0x7FFF DFFF.
– Address space between 0x8000 0000 and 0xDFFF FFFF, labelled "Reserved
Address Space".
– Reserved regions of the AHB and APB spaces. See
•
Unassigned AHB peripheral spaces. See
•
Unassigned APB peripheral spaces. See
Rev. 01 — 12 January 2006
Figure 2. For 8 kB SRAM device this is memory
Figure
Figure 4.
Table 2.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
UM10161
Chapter 2: Memory map
3.
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