Gpio Port 0 Pin Value Register (Iopin, Port 0: Io0Pin - 0Xe002 8000; Fiopin, Port 0: Fio0Pin - 0X3Fff C014); Koninklijke Philips Electronics N.v. 2006. All Rights Reserved - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
Aside from the 32-bit long and word only accessible FIOMASK register, every fast GPIO
port can also be controlled via several byte and half-word accessible registers listed in
Table
registers allow easier and faster access to the physical port pins.
Table 70: Fast GPIO port 0 Mask byte and half-word accessible register description
Register Register
name length (bits)
& access
FIO0MASK0 8 (byte)
FIO0MASK1 8 (byte)
FIO0MASK2 8 (byte)
FIO0MASK3 8 (byte)
FIO0MASKL 16
(half-word)
FIO0MASKU 16
(half-word)
8.4.3 GPIO port 0 Pin value register (IOPIN, Port 0: IO0PIN - 0xE002 8000;
FIOPIN, Port 0: FIO0PIN - 0x3FFF C014)
This register provides the value of port pins that are configured to perform only digital
functions. The register will give the logic value of the pin regardless of whether the pin is
configured for input or output, or as GPIO or an alternate digital function. As an example,
a particular port pin may have GPIO input or GPIO output, UART receive, and PWM
output as selectable functions. Any configuration of that pin will allow its current logic state
to be read from the IOPIN register.
If a pin has an analog function as one of its options, the pin state cannot be read if the
analog configuration is selected. Selecting the pin as an A/D input disconnects the digital
features of the pin. In that case, the pin value read in the IOPIN register is not valid.
Writing to the IOPIN register stores the value in the port output register, bypassing the
need to use both the IOSET and IOCLR registers to obtain the entire written value. This
feature should be used carefully in an application since it affects the entire port.
The legacy register is the IO0PIN, while the enhanced GPIOs are supported via the
FIO0PIN register. Access to a port pins via the FIOPIN register is conditioned by the
corresponding FIOMASK register (see
(FIOMASK, Port 0: FIO0MASK - 0x3FFF
Only pins masked with zeros in the Mask register (see
Mask register (FIOMASK, Port 0: FIO0MASK - 0x3FFF
current content of the Fast GPIO port pin value register.
User manual
70. Next to providing the same functions as the FIOMASK register, these additional
Address Description
0x3FFF C010 Fast GPIO Port 0 Mask register 0. Bit 0 in FIO0MASK0 register
corresponds to P0.0 ... bit 7 to P0.7.
0x3FFF C011 Fast GPIO Port 0 Mask register 1. Bit 0 in FIO0MASK1 register
corresponds to P0.8 ... bit 7 to P0.15.
0x3FFF C012 Fast GPIO Port 0 Mask register 2. Bit 0 in FIO0MASK2 register
corresponds to P0.16 ... bit 7 to P0.23.
0x3FFF C013 Fast GPIO Port 0 Mask register 3. Bit 0 in FIO0MASK3 register
corresponds to P0.24 ... bit 7 to P0.31.
0x3FFF C001 Fast GPIO Port 0 Mask Lower half-word register. Bit 0 in
FIO0MASKL register corresponds to P0.0 ... bit 15 to P0.15.
0x3FFF C012 Fast GPIO Port 0 Mask Upper half-word register. Bit 0 in
FIO0MASKU register corresponds to P0.16 ... bit 15 to P0.31.
Rev. 01 — 12 January 2006
Section 8.4.2 "Fast GPIO port 0 Mask register
C010)").
Section 8.4.2 "Fast GPIO port 0
C010)") will be correlated to the
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
UM10161
Chapter 8: GPIO
Reset
value
0x00
0x00
0x00
0x00
0x0000
0x0000
75