Mam Configuration; Register Description; Mam Control Register (Mamcr - 0Xe01F C000) - Philips LPC2101 User Manual

Philips Semiconductors
Volume 1
[1]
[2]
Table 31:
Data Memory Request Type
Sequential access, data in latches
Sequential access, data not in latches
Non-sequential access, data in latches
Non-sequential access, data not in latches Initiate Fetch
[1]

4.5 MAM configuration

After reset the MAM defaults to the disabled state. Software can turn memory access
acceleration on or off at any time. This allows most of an application to be run at the
highest possible performance, while certain functions can be run at a somewhat slower
but more predictable rate if more precise timing is required.

4.6 Register description

All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
Table 32:
Name
MAMCR Memory Accelerator Module Control Register.
MAMTIM Memory Accelerator Module Timing control.
[1]

4.7 MAM Control register (MAMCR - 0xE01F C000)

Two configuration bits select the three MAM operating modes, as shown in
Following Reset, MAM functions are disabled. Changing the MAM operating mode causes
the MAM to invalidate all of the holding latches, resulting in new reads of Flash information
as required.
User manual
Instruction prefetch is enabled in modes 1 and 2.
The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This
saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the
fetch timing value in MAMTIM to one clock.
MAM responses to data and DMA accesses of various types
The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This
saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the
fetch timing value in MAMTIM to one clock.
Summary of MAM registers
Description
Determines the MAM functional mode, that is, to
what extent the MAM performance enhancements
are enabled. See Table
Determines the number of clocks used for Flash
memory fetches (1 to 7 processor clocks).
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Rev. 01 — 12 January 2006
MAM Mode
0
[1]
Initiate Fetch
Initiate Fetch
[1]
Initiate Fetch
33.
UM10161
Chapter 4: MAM Module
1 2
[1]
Initiate Fetch Use Latched
Data
Initiate Fetch Initiate Fetch
[1]
Initiate Fetch Use Latched
Data
Initiate Fetch Initiate Fetch
Access Reset Address
[1]
value
R/W 0x0 0xE01F C000
R/W 0x07 0xE01F C004
Table
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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