Capture Registers (Cr0 - Cr3); Capture Control Register (Ccr, Timer2: T2Ccr - 0Xe007 0028 And Timer3: T3Ccr - 0Xe007 4028); User Manual - Philips LPC2101 User Manual

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16.5.9 Capture Registers (CR0 - CR3)

Each Capture register is associated with a device pin and may be loaded with the Timer
Counter value when a specified event occurs on that pin. The settings in the Capture
Control Register register determine whether the capture function is enabled, and whether
a capture event happens on the rising edge of the associated pin, the falling edge, or on
both edges.
16.5.10 Capture Control Register (CCR, TIMER2: T2CCR - 0xE007 0028 and
TIMER3: T3CCR - 0xE007 4028)
The Capture Control Register is used to control whether one of the four Capture Registers
is loaded with the value in the Timer Counter when the capture event occurs, and whether
an interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
description below, "n" represents the Timer number, 2 or 3.
Table 180: Capture Control Register (CCR, TIMER2: T2CCR - address 0xE007 0028 and TIMER3: T3CCR - address
0xE007 4028) bit description
Bit Symbol Value Description
0 CAP0RE 1
0
1 CAP0FE 1
0
2 CAP0I 1
0
3 CAP1RE 1
0
4 CAP1FE 1
0
5 CAP1I 1
0
6 CAP2RE 1
0
7 CAP2FE 1
0
8 CAP2I 1
0
[1]
15:9 -
[1]

User manual

Capture on CAPn.0 rising edge: a sequence of 0 then 1 on CAPn.0 will cause CR0 to
be loaded with the contents of TC.
This feature is disabled.
Capture on CAPn.0 falling edge: a sequence of 1 then 0 on CAPn.0 will cause CR0 to
be loaded with the contents of TC.
This feature is disabled.
Interrupt on CAPn.0 event: a CR0 load due to a CAPn.0 event will generate an interrupt. 0
This feature is disabled.
Capture on CAPn.1 rising edge: a sequence of 0 then 1 on CAPn.1 will cause CR1 to
be loaded with the contents of TC.
This feature is disabled.
Capture on CAPn.1 falling edge: a sequence of 1 then 0 on CAPn.1 will cause CR1 to
be loaded with the contents of TC.
This feature is disabled.
Interrupt on CAPn.1 event: a CR1 load due to a CAPn.1 event will generate an interrupt. 0
This feature is disabled.
Capture on CAPn.2 rising edge: A sequence of 0 then 1 on CAPn.2 will cause CR2 to
be loaded with the contents of TC.
This feature is disabled.
Capture on CAPn.2 falling edge: a sequence of 1 then 0 on CAPn.2 will cause CR2 to
be loaded with the contents of TC.
This feature is disabled.
Interrupt on CAPn.2 event: a CR2 load due to a CAPn.2 event will generate an interrupt. 0
This feature is disabled.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
On TIMER2/3, CAPn.3 is disabled and values for CAP3RE, CAP3FE, and CAP3I are not defined.
Rev. 01 — 12 January 2006
UM10161
Chapter 16: Timer2 and Timer3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Reset
value
0
0
0
0
0
0
NA
207