Table 127: Can Interrupt And Capture Register (Canicr - 0Xe00X X00C) - Philips LPC2194 User Manual

Philips Semiconductors
ARM-based Microcontroller
Table 128: CAN Interrupt and Capture Register (CANICR - 0xE00x x00C)
CANICR Name Function
1: Receive Interrupt -- this bit is set whenever the RBS bit in CANSR and the RIE
0 RI
bit in CANIER are both 1, indicating that a received message is available.=.
1: Transmit Interrupt 1 -- this bit is set when the TBS1 bit in CANSR goes from 0
1 TI1
to 1, indicating that Transmit buffer 1 is available, and the TIE1 bit in CANIER is 1.
1: Error Warning Interrupt -- this bit is set on every change (set or clear) of the Error
2 EI Status or Bus Status bit in CANSR, if the EIE bit in CAN is 1 at the time of the
change.
1: Data Overrun Interrupt -- this bit is set when the DOS bit in CANSR goes from
3 DOI
0 to 1, if the DOIE bit in CANIE is 1.
1: Wake-Up Interrupt: this bit is set if the CAN controller is sleeping and bus activity
4 WUI
is detected, if the WUIE bit in CANIE is 1.
1: Error Passive Interrupt -- this bit is set if the EPIE bit in CANIE is 1, and the CAN
5 EPI controller switches between Error Passive and Error Active mode in either
direction.
1: Arbitration Lost Interrupt -- this bit is set if the ALIE bit in CANIE is 1, and the
6 ALI
CAN controller loses arbitration while attempting to transmit.
1: Bus Error Interrupt -- this bit is set if the BEIE bit in CANIE is 1, and the CAN
7 BEI
controller detects an error on the bus.
1: ID Ready Interrupt -- this bit is set if the IDIE bit in CANIE is 1, and a CAN
8 IDI
Identifier has been received.
1: Transmit Interrupt 2 -- this bit is set when the TBS2 bit in CANSR goes from 0
9 TI2
to 1, indicating that Transmit buffer 2 is available, and the TIE2 bit in CANIER is 1.
1: Transmit Interrupt 1 -- this bit is set when the TBS3 bit in CANSR goes from 0
10 TI3
to 1, indicating that Transmit buffer 3 is available, and the TIE3 bit in CANIER is 1.
CAN Controllers and Acceptance Filter
LPC2119/2129/2292/2294
195
Preliminary User Manual
Reset Value RM Set
0 0
0 0
0 X
0 0
0 0
0 0
0 0
0 X
0 0
0 0
0 0
May 03, 2004