Architecture - Philips LPC2194 User Manual

Philips Semiconductors Preliminary User Manual
ARM-based Microcontroller LPC2119/2129/2194/2292/2294

ARCHITECTURE

The architecture of the UART1 is shown below in the block diagram.
The VPB interface provides a communications link between the CPU or host and the UART1.
The UART1 receiver block, U1Rx, monitors the serial input line, RxD1, for valid input. The UART1 Rx Shift Register (U1RSR)
accepts valid characters via RxD1. After a valid character is assembled in the U1RSR, it is passed to the UART1 Rx Buffer
Register FIFO to await access by the CPU or host via the generic host interface.
The UART1 transmitter block, U1Tx, accepts data written by the CPU or host and buffers the data in the UART1 Tx Holding
Register FIFO (U1THR). The UART1 Tx Shift Register (U1TSR) reads the data stored in the U1THR and assembles the data to
transmit via the serial output pin, TxD1.
The UART1 Baud Rate Generator block, U1BRG, generates the timing enables used by the UART1 Tx block. The U1BRG clock
input source is the VPB clock (pclk). The main clock is divided down per the divisor specified in the U1DLL and u1DLM registers.
This divided down clock is a 16x oversample clock, NBAUDOUT.
The modem interface contains registers U1MCR and U1MSR. This interface is responsible for handshaking between a modem
peripheral and the UART1.
The interrupt interface contains registers U1IER and U1IIR. The interrupt interface receives several one clock wide enables from
the U1Tx, U1Rx and modem blocks.
Status information from the U1Tx and U1Rx is stored in the U1LSR. Control information for the U1Tx and U1Rx is stored in the
U1LCR.
UART1 164 May 03, 2004