Philips LPC2194 User Manual page 258

Philips Semiconductors
ARM-based Microcontroller
Watchdog Mode Register (WDMOD - 0xE0000000)
The WDMOD register controls the operation of the Watchdog as per the combination of WDEN and RESET bits.
WDEN
0
1
1
Once the WDEN and/or WDRESET bits are set they can not be cleared by software. Both flags are cleared by an external reset
or a Watchdog timer underflow.
WDTOF The Watchdog time-out flag is set when the Watchdog times out. This flag is cleared by software.
WDINT The Watchdog interrupt flag is set when the Watchdog times out. This flag is cleared when any reset occurs.
Table 194: Watchdog Mode Register (WDMOD - 0xE0000000)
WDMOD Function
0 WDEN
1 WDRESET
2 WDTOF
3 WDINT
7:4 Reserved
Watchdog Timer Constant Register (WDTC - 0xE0000004)
The WDTC register determines the time-out value. Every time a feed sequence occurs the WDTC content is reloaded in to the
Watchdog timer. It's a 32-bit register with 8 LSB set to 1 on reset. Writing values below 0xFF will cause 0xFF to be loaded to the
WDTC. Thus the minimum time-out interval is t
WDTC Function
31:0 Count
Watchdog
WDRESET
X Debug/Operate without the Watchdog running
0 Debug with the Watchdog interrupt but no WDRESET
1 Operate with the Watchdog interrupt and WDRESET
Watchdog interrupt enable bit (Set only)
Watchdog reset enable bit (Set Only)
Watchdog time-out flag
Watchdog interrupt flag (Read Only)
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
x 256 x 4.
pclk
Watchdog time-out interval
LPC2119/2129/2194/2292/2294
Description
Description
258
Preliminary User Manual
Reset Value
0
0
0 (Only after
external reset)
0
NA
Reset
Value
0xFF
May 03, 2004