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Philips Semiconductors
ARM-based Microcontroller
Table 84: UART0 Line Status Register Bit Descriptions (U0LSR - 0xE000C014, Read Only)
U0LSR
Function
0: U0RBR is empty
Receiver
1: U0RBR contains valid data
0
Data Ready
U0LSR0 is set when the U0RBR holds an unread character and is cleared when the
(RDR)
UART0 RBR FIFO is empty.
0: Overrun error status is inactive.
1: Overrun error status is active.
Overrun
The overrun error condition is set as soon as it occurs. An U0LSR read clears U0LSR1.
1
Error
U0LSR1 is set when UART0 RSR has a new character assembled and the UART0 RBR
(OE)
FIFO is full. In this case, the UART0 RBR FIFO will not be overwritten and the character
in the UART0 RSR will be lost.
0: Parity error status is inactive.
1: Parity error status is active.
Parity Error
2
When the parity bit of a received character is in the wrong state, a parity error occurs. An
(PE)
U0LSR read clears U0LSR2. Time of parity error detection is dependent on U0FCR0.
A parity error is associated with the character being read from the UART0 RBR FIFO.
0: Framing error status is inactive.
1: Framing error status is active.
When the stop bit of a received character is a logic 0, a framing error occurs. An U0LSR
Framing
read clears U0LSR3. The time of the framing error detection is dependent on U0FCR0.
3
Error
A framing error is associated with the character being read from the UART0 RBR FIFO.
(FE)
Upon detection of a framing error, the Rx will attempt to resynchronize to the data and
assume that the bad stop bit is actually an early start bit. However, it cannot be assumed
that the next received byte will be correct even if there is no Framing Error.
0: Break interrupt status is inactive.
1: Break interrupt status is active.
When RxD0 is held in the spacing state (all 0's) for one full character transmission (start,
Break
data, parity, stop), a break interrupt occurs. Once the break condition has been detected,
4
Interrupt
the receiver goes idle until RxD0 goes to marking state (all 1's). An U0LSR read clears
(BI)
this status bit. The time of break detection is dependent on U0FCR0.
The break interrupt is associated with the character being read from the UART0 RBR
FIFO.
Transmitter
0: U0THR contains valid data.
Holding
1: U0THR is empty.
5
Register
THRE is set immediately upon detection of an empty UART0 THR and is cleared on a
Empty
U0THR write.
(THRE)
0: U0THR and/or the U0TSR contains valid data.
Transmitter
1: U0THR and the U0TSR are empty.
6
Empty
TEMT is set when both U0THR and U0TSR are empty; TEMT is cleared when either the
(TEMT)
U0TSR or the U0THR contain valid data.
0: U0RBR contains no UART0 Rx errors or U0FCR0=0.
Error in Rx
1: UART0 RBR contains at least one UART0 Rx error.
7
FIFO
U0LSR7 is set when a character with a Rx error such as framing error, parity error or
(RXFE)
break interrupt, is loaded into the U0RBR. This bit is cleared when the U0LSR register is
read and there are no subsequent errors in the UART0 FIFO.
UART0
LPC2119/2129/2194/2292/2294
Description
147
Preliminary User Manual
Reset
Value
0
0
0
0
0
1
1
0
May 03, 2004
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