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Philips Semiconductors
ARM-based Microcontroller
MEMORY MAPPING CONTROL
The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x00000000. This
allows code running in different memory spaces to have control of the interrupts.
Memory Mapping Control Register (MEMMAP - 0xE01FC040)
Table 19: MEMMAP Register
Address
Name
0xE01FC040
MEMMAP
Table 20: Memory Mapping Control Register (MEMMAP - 0xE01FC040)
MEMMAP
Function
1:0
MAP1:0
7:2
Reserved
*: The hardware reset value of the MAP bits is 00 for LPC2119/2129/2194/2292/2294 parts. The apparent reset value that the
user will see will be altered by the Boot Loader code, which always runs initially at reset. User documentation will reflect this
difference.
Memory Mapping Control Usage Notes
Memory Mapping Control simply selects one out of three available sources of data (sets of 64 bytes each) necessary for handling
ARM exceptions (interrupts).
For example, whenever a Software Interrupt request is generated, ARM core will always fetch 32-bit data "residing" on 0x0000
0008 (see Table 3, "ARM Exception Vector Locations," on page 52). This means that when MEMMAP[1:0]=10 (User RAM Mode),
read/fetch from 0x0000 0008 will provide data stored in 0x4000 0008. If MEMMAP[1:0]=01 (User Flash Mode), read/fetch from
0x0000 0008 will provide data stored in on-chip Flash location 0x0000 0008. In case of MEMMAP[1:0]=00 (Boot Loader Mode),
read/fetch from 0x0000 0008 will provide data availble also at 0x7FFF E008 (Boot Block remapped from on-chip Flash memory).
System Control Block
Memory mapping control. Selects whether the ARM interrupt vectors are read
from the Flash Boot Block, User Flash or RAM.
00: Boot Loader Mode. Interrupt vectors are re-mapped to Boot Block.
01: User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
10: User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
11: User External memory Mode. Interrupt vectors are re-mapped to external memory.
This mode is available in L2292/2294 only and must not be specified when
LPC2119/2129/2194 are used.
Warning: Improper setting of this value may result in incorrect operation of the device.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
LPC2119/2129/2194/2292/2294
Description
Description
74
Preliminary User Manual
Access
R/W
Reset
Value*
0
NA
May 03, 2004
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