Table of Contents
Advertisement
Philips Semiconductors
ARM-based Microcontroller
Table 56: Pin description for LPC2292/2294
Pin
LQFP144
Name
Pin #
40
36
35
30
29
28
27
97
96
TD1
22
RESET
135
XTAL1
142
XTAL2
141
3, 9, 26, 38, 54,
V
67, 79, 93, 103,
SS
107, 111, 128
V
139
SSA
V
138
ssA_PLL
Pin Configuration
Type
P3.23
A23
I/O
XCLK
O
O
P3.24
CS3
O
P3.25
CS2
P3.26
CS1
O
P3.27
WE
O
P3.28
BLS3
O
AIN7
I
P3.29
BLS2
O
AIN6
I
P3.30
BLS1
O
P3.31
BLS0
O
TD1:CAN1 transmitter output.Pin is 5 V tolerant with built-in pull-up.
O
External Reset input: A LOW on this pin resets the device, causing I/O ports and
I
peripherals to take on their default states, and processor execution to begin at address 0.
TTL with hysteresis, 5V tolerant.
I
Input to the oscillator circuit and internal clock generator circuits.
O
Output from the oscillator amplifier.
I
Ground: 0V reference.
Analog Ground: 0V reference. This should nominally be the same voltage as V
I
should be isolated to minimize noise and error.
PLL Analog Ground: 0V reference. This should nominally be the same voltage as V
I
should be isolated to minimize noise and error.
LPC2119/2129/2194/2292/2294
Description
External memory address line 23.
Clock output.
Low-active Chip Select 3 signal.
(Bank 3 addresses range 8300 0000 - 83FF FFFF)
Low-active Chip Select 2 signal.
(Bank 2 addresses range 8200 0000 - 82FF FFFF)
Low-active Chip Select 1 signal.
(Bank 1 addresses range 8100 0000 - 81FF FFFF)
Low-active Write enable signal.
Low-active Byte Lane Select signal (Bank 3).
A/D converter, input 7. This analog input is always connected to
its pin.
Low-active Byte Lane Select signal (Bank 2).
A/D converter, input 6. This analog input is always connected to
its pin.
Low-active Byte Lane Select signal (Bank 1).
Low-active Byte Lane Select signal (Bank 0).
124
Preliminary User Manual
but
SS,
but
SS,
May 03, 2004
Advertisement
Table of Contents
