Philips LPC2194 User Manual page 172

Philips Semiconductors
ARM-based Microcontroller
2
I C Control Set Register (I2CONSET - 0xE001C000)
AA is the Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA) will be returned during the acknowledge
clock pulse on the SCL line on the following situations:
1. The address in the Slave Address Register has been received.
2. The general call address has been received while the general call bit(GC) in I2ADR is set.
3. A data byte has been received while the I
4. A data byte has been received while the I
The AA bit can be cleared by writing 1 to the AAC bit in the I2CONCLR register. When AA is 0, a not acknowledge (high level to
SDA) will be returned during the acknowledge clock pulse on the SCL line on the following situations:
1. A data byte has been received while the I
2. A data byte has been received while the I
2
SI is the I C Interrupt Flag. This bit is set when one of the 25 possible I
only be used to indicate a start condition at an idle slave device, or a stop condition at an idle master device (if it is waiting to use
2
the I C bus). SI is cleared by writing a 1 to the SIC bit in I2CONCLR register.
STO is the STOP flag. Setting this bit causes the I
error condition in slave mode. When STO is 1 in master mode, a STOP condition is transmitted on the I
detects the STOP condition, STO is cleared automatically.
In slave mode, setting this bit can recover from an error condition. In this case, no STOP condition is transmitted to the bus. The
hardware behaves as if a STOP condition has been received and it switches to "not addressed" slave receiver mode. The STO
flag is cleared by hardware automatically.
STA is the START flag. Setting this bit causes the I
a repeated START condition if it is already in master mode.
2
When STA is 1and the I C interface is not already in master mode, it enters master mode, checks the bus and generates a
START condition if the bus is free. If the bus is not free, it waits for a STOP condition (which will free the bus) and generates a
START condition after a delay of a half clock period of the internal clock generator. If the I
and data has been transmitted or received, it transmits a repeated START condition. STA may be set at any time, including when
2
the I C interface is in an addressed slave mode.
STA can be cleared by writing 1 to the STAC bit in the I2CONCLR register. When STA is 0, no START condition or repeated
START condition will be generated.
If STA and STO are both set, then a STOP condition is transmitted on the I
transmits a START condition thereafter. If the I
transmitted on the bus.
I2C Interface
2
C is in the master receiver mode.
2
C is in the addressed slave receiver mode
2
C is in the master receiver mode.
2
C is in the addressed slave receiver mode.
2
C states is entered. Typically, the I
2
C interface to transmit a STOP condition in master mode, or recover from an
2
C interface to enter master mode and transmit a START condition or transmit
2
C interface is in slave mode, an internal STOP condition is generated, but is not
172
LPC2119/2129/2194/2292/2294
2
C interface is already in master mode
2
C bus if it the interface is in master mode, and
Preliminary User Manual
2
C interrupt should
2
C bus. When the bus
May 03, 2004