Example Timer Operation; Figure 39: A Timer Cycle In Which Pr=2, Mrx=6, And Both Interrupt And Reset On Match Are Enabled; Figure 40: A Timer Cycle In Which Pr=2, Mrx=6, And Both Interrupt And Stop On Match Are Enabled - Philips LPC2194 User Manual

Philips Semiconductors
ARM-based Microcontroller

EXAMPLE TIMER OPERATION

Figure 39 shows a timer configured to reset the count and generate an interrupt on match. The prescaler is set to 2 and the match
register set to 6. At the end of the timer cycle where the match occurs, the timer count is reset. This gives a full length cycle to
the match value. The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match
value.
Figure 40 shows a timer configured to stop and generate an interrupt on match. The prescaler is again set to 2 and the match
register set to 6. In the next clock after the timer reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.
pclk
Prescale Counter
Timer Counter
Timer Counter
Reset
Interrupt

Figure 39: A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled.

pclk
Prescale Counter
Timer Counter
TCR[0]
(Counter Enable)
Interrupt

Figure 40: A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled.

Timer0 and Timer1
2 0 1 2
4 5
2 0 1 2
4 5
1
LPC2119/2129/2194/2292/2294
0 1 2 0
6
0
6
0
221
Preliminary User Manual
1 2 0 1
0 1
May 03, 2004