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Philips Semiconductors
ARM-based Microcontroller
TYPICAL BUS SEQUENCES
Following figures show typical external read and write access cycles. XCLK is the clock signal avalable on P3.23. While not
necessary used by external memory, In these examples it is used to provide the time reference (XCLK and CCLK were set to
have the same frequency).
Figure 10: External memory read access (WST1=0 and WST1=1 examples)
Figure 11: External memory write access (WST2=0 and WST2=1 examples)
Figure 10 and Figure 11 are showing typical read and write accesses to external memory. However, variations can be noticed in
some particular cases.
For example, when the first read access to the memory bank that has just been selected is performed, CS and OE lines may
become low one XCLK cycle earlier than it is shown in Figure 10.
Likewise, in a sequence of several consecutive write accesses to SRAM, the last write access will look like those shown in Figure
11. On the other hand, leading write cycles in that case will have data valid one cycle longer. Also, isloated write access will be
identical to the one in Figure 11.
External Memory Controller (EMC)
XCLK
CS
OE
WE/BLS
Addr
valid address
Data
change
XCLK
CS
OE
WE/BLS
Addr
Data
change
XCLK
CS
OE
WE/BLS
Addr
valid address
Data
XCLK
CS
OE
WE/BLS
Addr
Data
LPC2119/2129/2194/2292/2294
1 wait state (WST1=0)
valid data
2 wait states (WST1=1)
valid address
valid data
WST2=0
valid data
WST2=1
valid address
valid data
61
Preliminary User Manual
May 03, 2004
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