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Philips Semiconductors
ARM-based Microcontroller
UART1 Interrupt Identification Register (U1IIR - 0xE0010008, Read Only)
The U1IIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during an
U1IIR access. If an interrupt occurs during an U1IIR access, the interrupt is recorded for the next U1IIR access.
Table 93: UART1 Interrupt Identification Register Bit Descriptions (IIR - 0xE0010008, Read Only)
U1IIR
Function
Interrupt
0
Pending
Interrupt
3:1
Identification
5:4
Reserved
7:6
FIFO Enable
Interrupts are handled as described in Table 94. Given the status of U1IIR[3:0], an interrupt handler routine can determine the
cause of the interrupt and how to clear the active interrupt. The U1IIR must be read in order to clear the interrupt prior to exiting
the Interrupt Service Routine.
The UART1 RLS interrupt (U1IIR3:1=011) is the highest priority interrupt and is set whenever any one of four error conditions
occur on the UART1Rx input: overrun error (OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART1 Rx
error condition that set the interrupt can be observed via U1LSR4:1. The interrupt is cleared upon an U1LSR read.
The UART1 RDA interrupt (U1IIR3:1=010) shares the second level priority with the CTI interrupt (U1IIR3:1=110). The RDA is
activated when the UART1 Rx FIFO reaches the trigger level defined in U1FCR7:6 and is reset when the UART1 Rx FIFO depth
falls below the trigger level. When the RDA interrupt goes active, the CPU can read a block of data defined by the trigger level.
The CTI interrupt (U1IIR3:1=110) is a second level interrupt and is set when the UART1 Rx FIFO contains at least one character
and no UART1 Rx FIFO activity has occurred in 3.5 to 4.5 character times. Any UART1 Rx FIFO activity (read or write of UART1
RSR) will clear the interrupt. This interrupt is intended to flush the UART1 RBR after a message has been received that is not a
multiple of the trigger level size. For example, if a peripheral wished to send a 105 character message and the trigger level was
10 characters, the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts
(depending on the service routine) resulting in the transfer of the remaining 5 characters.
UART1
0: At least one interrupt is pending.
1: No pending interrupts.
Note that U1IIR0 is active low. The pending interrupt can be determined by evaluating
U1IIR3:1.
011: 1. Receive Line Status (RLS)
010: 2a.Receive Data Available (RDA)
110: 2b.Character Time-out Indicator (CTI)
001: 3. THRE Interrupt.
000: 4. Modem Interrupt.
U1IER3 identifies an interrupt corresponding to the UART1 Rx FIFO and modem signals.
All other combinations of U1IER3:1 not listed above are reserved (100,101,111).
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
These bits are equivalent to U1FCR0.
LPC2119/2129/2194/2292/2294
Description
156
Preliminary User Manual
Reset
Value
1
0
NA
0
May 03, 2004
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