Table 74: Uart0 Receiver Buffer Register (U0Rbr - 0Xe000C000 When Dlab = 0, Read Only); Table 75: Uart0 Transmit Holding Register (U0Thr - 0Xe000C000 When Dlab = 0, Write Only); Table 76: Uart0 Divisor Latch Lsb Register (U0Dll - 0Xe000C000 When Dlab = 1); Table 77: Uart0 Divisor Latch Msb Register (U0Dlm - 0Xe000C004 When Dlab = 1) - Philips LPC2194 User Manual

Philips Semiconductors
ARM-based Microcontroller
Table 75: UART0 Receiver Buffer Register (U0RBR - 0xE000C000 when DLAB = 0, Read Only)
U0RBR Function
Receiver Buffer
7:0
Register
UART0 Transmitter Holding Register (U0THR - 0xE000C000 when DLAB = 0, Write Only)
The U0THR is the top byte of the UART0 Tx FIFO. The top byte is the newest character in the Tx FIFO and can be written via
the bus interface. The LSB represents the first bit to transmit.
The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the U0THR. The U0THR is always Write Only.
Table 76: UART0 Transmit Holding Register (U0THR - 0xE000C000 when DLAB = 0, Write Only)
U0THR Function
Transmit
7:0
Holding Register
UART0 Divisor Latch LSB Register (U0DLL - 0xE000C000 when DLAB = 1)
UART0 Divisor Latch MSB Register (U0DLM - 0xE000C004 when DLAB = 1)
The UART0 Divisor Latch is part of the UART0 Baud Rate Generator and holds the value used to divide the VPB clock (pclk) in
order to produce the baud rate clock, which must be 16x the desired baud rate. The U0DLL and U0DLM registers together form
a 16 bit divisor where U0DLL contains the lower 8 bits of the divisor and U0DLM contains the higher 8 bits of the divisor. A 'h0000
value is treated like a 'h0001 value as division by zero is not allowed.The Divisor Latch Access Bit (DLAB) in U0LCR must be
one in order to access the UART0 Divisor Latches.
Table 77: UART0 Divisor Latch LSB Register (U0DLL - 0xE000C000 when DLAB = 1)
U0DLL Function
Divisor Latch
7:0
LSB Register
Table 78: UART0 Divisor Latch MSB Register (U0DLM - 0xE000C004 when DLAB = 1)
U0DLM Function
Divisor Latch
7:0
MSB Register
UART0
The UART0 Receiver Buffer Register contains the oldest received byte in the UART0 Rx
FIFO.
Writing to the UART0 Transmit Holding Register causes the data to be stored in the
UART0 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and
the transmitter is available.
The UART0 Divisor Latch LSB Register, along with the U0DLM register, determines the
baud rate of the UART0.
The UART0 Divisor Latch MSB Register, along with the U0DLL register, determines the
baud rate of the UART0.
LPC2119/2129/2194/2292/2294
Description
Description
Description
Description
142
Preliminary User Manual
Reset
Value
un-
defined
Reset
Value
N/A
Reset
Value
0x01
Reset
Value
0
May 03, 2004